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Abstract
We present a proof-of-concept demonstration of a Ge/a-Si hybrid photonic integrated circuit platform utilizing a high-quality Ge-on-insulator (GeOI) wafer fabricated by wafer bonding technology. Amorphous Si (a-Si) formed by PECVD is found to be a promising alternative to conventional Si passive waveguides on a SiO2 BOX. Taking advantage of the high crystal quality of the Ge active layer and the easy fabrication of an a-Si waveguide, a low-dark-current Ge waveguide PIN photodetector monolithically integrated with an a-Si passive waveguide is successfully demonstrated on a GeOI wafer.
© 2018 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. Introduction
In recent decades, there has been significant progress in the field of Si photonics. Among them, the introduction of a Ge thin film into Si-based platforms has proved to be a successful approach, which enables not only new device functionalities but, more importantly, the realization of various advanced systems on a single chip [1–4]. Ge has many advantageous optical properties over Si. It exhibits strong optical absorption at wavelengths from 1.3 μm to 1.55 μm, making it ideal for photodetectors (PDs) in optical fiber communications [5–7]. A large electro-absorption effect has also been observed in Ge, making it promising material for realizing efficient optical intensity modulators [8,9]. Although Ge is an indirect-bandgap semiconductor similar to Si, its direct bandgap is only 0.14 eV above the indirect bandgap at the Γ valley. With the help of emerging band structure engineering technologies, it is even possible to fabricate practical Ge-based light sources [10–13]. Thus, by realizing Ge active photonic devices and Si passive devices, integration between Ge and Si provides a promising means of achieving a cost-effective highly functionalized photonic integrated circuit (PIC) platform, suitable for a wide range of applications.
To integrate Ge with Si, the conventional approach involves the epitaxial growth of Ge on Si. However, the large lattice mismatch of 4.2% between Ge and Si usually results in a high density of dislocation defects in the grown Ge layer as well as at the Ge/Si interface, which may serve as undesirable generation/recombination centers, degrading the Ge crystal quality and consequently the device performance [1]. Although many attempts have been made to improve the quality of the epitaxial Ge layer, including methods such as two-step growth [14], the use of a graded SiGe buffer layer [15], aspect ratio trapping [16,17], and annealing technologies [18,19], it is still difficult to get rid of all the defects generated during epitaxial growth and achieve a Ge thin film with sufficiently high quality.
In addition to the advanced epitaxial growth methods with high process complexity and cost, wafer bonding technology is also very promising for high-quality Ge integration with Si. By transferring a Ge thin film from a Ge bulk wafer to a Si substrate, the crystal defects due to lattice mismatch can be avoided. Previously, we have reported the successful fabrication of a high-quality Ge-on-insulator (GeOI) wafer by combining wafer bonding and Smart-CutTM technologies [20]. The fabricated GeOI wafer contains a 2-μm-thick buried oxide layer (BOX), similar to that in Si-on-insulator (SOI) wafers, enabling strong optical confinement in the Ge active layer. Employing the GeOI wafer, we have demonstrated Si-photonics-like Ge PICs for mid-infrared photonics [21]. This strong optical confinement in the GeOI wafer is also beneficial for near-infrared (NIR) applications including Ge-based lasers, modulators, and PDs. Thus, we propose a new PIC platform consisting of Ge-based active photonic devices on a GeOI wafer interconnected with amorphous Si (a-Si) passive waveguides.
Figure 1 illustrates the concept of Ge/a-Si hybrid PICs built on a GeOI wafer. A Ge device layer with high crystal quality as well as strong optical confinement in the GeOI wafer fabricated by wafer bonding allows us to develop high-performance, low-power, and compact PICs for NIR wavelengths. In this paper, we present a proof-of-concept demonstration of a Ge/a-Si hybrid platform on a GeOI wafer. First, we investigate Ge waveguide PDs on a GeOI wafer. Then, monolithic integration between an a-Si waveguide and a Ge PD is achieved by applying an optimized integration process, showing the feasibility of GeOI-based PICs with a-Si waveguide interconnects for NIR photonics.
2. a-Si passive waveguides
Amorphous Si is known for its process simplicity and design flexibility in integrated optics [22–24]. To examine its capability of replacing conventional Si waveguides for interconnection on a GeOI substrate, an a-Si waveguide is fabricated on a 2-μm-thick SiO2-covered Si substrate, which is also used in the GeOI wafer fabrication.
For ease of measurement, a pair of focusing grating couplers is designed at both ends of the a-Si waveguide, following a similar design methodology to that for conventional SOI grating couplers [25]. Assuming the refractive index value of a-Si to be 3.7 [24], a grating pitch of 560 nm, filling factor of 0.5, incidence angle of 9° and etching depth of 70 nm are applied as the design parameters of the grating couplers with an a-Si layer thickness of 220 nm with the aim of achieving at a central wavelength of 1550 nm. In addition, grating couplers and Si waveguides are also fabricated on an SOI wafer containing a 220-nm-thick Si top layer and a 2-μm-thick SiO2 BOX for comparison.
To fabricate the a-Si waveguide, a SiO2-covered Si (SiO2/Si) substrate is ultrasonically cleaned in deionized water. Then, a 220-nm-thick a-Si layer is directly deposited on the SiO2 surface by plasma-enhanced chemical vapor deposition (PECVD) at 250 °C using 5% SiH4 diluted with He gas. By combining electron beam (EB) lithography and inductively coupled plasma (ICP) dry etching with a mixed gas of SF6 and CHF3, gratings with an etching depth of approximately 70 nm are defined on the a-Si layer. After that, a 10-nm-thick SiO2 layer is deposited on the a-Si surface by PECVD to serve as a hard mask [26], which is followed by waveguide formation using EB lithography and ICP dry etching. Finally, the bare a-Si waveguide is covered with a SiO2 layer for passivation. Note that similar fabrication processes are applied to fabricate the SOI waveguides, with only a small difference between the dry etching rates for a-Si and Si.
Figure 2(a) shows a microscope plan-view image of a fabricated a-Si waveguide integrated with focusing grating couplers. To characterize the transmission property of the a-Si waveguide, the optical input from a commercial tunable laser is coupled to an input grating coupler through a single mode fiber (SMF). Then, the output light is again coupled from an output grating coupler to another SMF and the transmission power is measured by an InGaAs photodetector. Figure 2(b) shows a typical transmission spectrum of a 1-μm-wide 0.9-mm-long a-Si waveguide coupled with a pair of grating couplers.
Fig. 2 (a) Microscope plan-view image of fabricated a-Si waveguide integrated with focusing grating coupler. The inset shows a zoom-in view of the a-Si grating coupler. (b) Typical transmission spectrum of a-Si waveguide coupled with a pair of grating couplers.
A blue shift of the center wavelength is observed in the transmission spectrum, which may have resulted from a smaller refractive index of the fabricated a-Si device than that previously assumed. By measuring the transmission spectra of a-Si waveguides with lengths ranging from 0.9 mm to 6.1 mm and waveguide widths ranging from 600 nm to 2 μm, the propagation loss in a-Si waveguides as a function of the waveguide width is obtained by the cutback method, as shown in Fig. 3(a). We also obtain the corresponding results from Si waveguides for comparison, which are shown in Fig. 3(b).
Fig. 3 (a) Propagation losses in (a) a-Si and (b) Si waveguides as functions of waveguide width obtained by the cutback method. Fitting curves are also plotted in the figures and the estimated waveguide sidewall roughness values are given.
It is found that the a-Si waveguides show slightly larger propagation losses than the Si waveguides. Meanwhile, the increase in the propagation loss in a-Si waveguides is faster than that in the Si waveguides as the waveguide width decreases.
According to Ref [27], the lower limit of the propagation loss with increasing width of the waveguide is determined by the scattering from the top and bottom surfaces of the waveguide, while the remnant propagation loss is dominated by the scattering from the sidewalls. In addition, the propagation loss is inversely proportional to the fourth power of the waveguide width and proportional to the square of the room mean square (RMS) sidewall roughness. Thus, the sidewall roughness of the fabricated waveguides is evaluated by fitting the obtained propagation losses as functions of the widths of the a-Si and Si waveguides, which are also plotted in Fig. 3. It is found that the RMS sidewall roughness in the a-Si waveguides is 8 nm, slightly larger than that in the Si waveguides of 7 nm. The difference in the sidewall roughness may have resulted from the dry etching process, during which a-Si shows slightly higher etching rate than Si. This explains faster increase in the propagation loss in the a-Si waveguides as the waveguide width decreases.
Furthermore, the lower limit of the propagation loss in the a-Si waveguides is also slightly larger than that in the Si ones, indicating stronger scattering from the top and bottom surfaces. To understand this result, the surface morphologies of the waveguides are studied by atomic force microscope (AFM) using unpatterned samples. It is found that the as-deposited a-Si layer has an RMS surface roughness of 0.5 nm over a 10 × 10 μm2 area, which is larger than that of the conventional SOI wafer of 0.2 nm. This surface roughness contributes to the larger propagation loss in the a-Si waveguides, which is expected to be reduced by either optimizing the a-Si deposition conditions or performing chemical mechanical polishing (CMP) on the a-Si surface. Nevertheless, acceptable propagation losses have been achieved in the a-Si waveguides, which suggests that they are a suitable alternative to Si waveguides for passive interconnections on a GeOI substrate.
3. Ge rib waveguide PDs on high-quality GeOI wafer
A high-quality Ge layer is of great importance for achieving a high-performance Ge PD. To obtain a high-quality GeOI wafer, a Ge thin film from a Ge bulk wafer is transferred onto a 2-μm-thick SiO2 layer on a Si substrate by combining wafer bonding and Smart-CutTM technologies. An optimized thermal annealing process is conducted on the GeOI wafer after CMP for surface planarization to further improve the Ge crystal quality. Details of the GeOI wafer fabrication are given in Ref [20]. Hall measurement reveals a high hole mobility of over 2000 cm2/Vs and a low carrier density of approximately 1 × 1016 cm−3 in the Ge layer on the fabricated GeOI wafer, which are desirable for various Ge-based functional devices. To further investigate the Ge crystal quality, transmission electron microscopy (TEM) observations are performed on the GeOI substrate.
Figure 4 shows a cross-sectional TEM image of the fabricated GeOI wafer. The inset shows a zoom-in view of the Ge layer close to the interface between the Ge and the SiO2 BOX.
Fig. 4 Cross-sectional TEM image of the fabricated GeOI wafer. The inset shows a zoom-in view of the Ge layer close to the interface between the Ge and the SiO2 BOX.
No obvious defects such as dislocations exist in the Ge layer on the GeOI substrate. In addition, a plan-view TEM observation is also performed on the Ge surface to check for the existence of crystal defects, as shown in Fig. 5.
From the plan-view TEM image, a clear Ge surface with no crystal defects is observed over a 10 × 10 μm2 area, which means that the defect density of the Ge layer on the GeOI substrate is much lower than 1 × 106 cm−2. This result suggests that a Ge layer with sufficiently high crystal quality can be achieved in the wafer-bonded GeOI wafer, providing a solid foundation for realizing high-performance Ge active devices in future.
Next, a Ge rib waveguide PD is fabricated to study the intrinsic properties of a Ge PD on a GeOI wafer. Figure 6 illustrates the fabrication process flow of the Ge rib waveguide PD. After precleaning the GeOI substrate, a Ge layer is thinned to a thickness of 300 nm by reactive ion etching (RIE) using CF4 gas. The Ge rib waveguide structure is defined by EB lithography and RIE dry etching. Then, ion implantations of phosphorus (P) and boron (B) are conducted on the Ge slab to form n+- and p+-doped regions, respectively. For dopant activation, thermal annealing is carried out in nitrogen ambient at 600 °C for 1 min. After isolating the devices by dry etching, GeOx passivation is performed on the Ge surface to improve its surface condition [28,29], which is followed by the deposition of a 300-nm-thick SiO2 layer on the surface by PECVD for protection. Finally, via holes are opened by BHF wet etching and nickel contacts are formed by thermal evaporation.
To evaluate the electrical properties of the Ge rib waveguide PD, its current-voltage (I-V) characteristic is measured. Figure 7 shows a typical I-V curve of a 50-μm-long isolated Ge rib waveguide with a lateral p-i-n junction.
Despite the relatively long PD length, the fabricated device exhibits a low dark current of 14 nA under −1 V bias. This low dark current is attributable to the superior GeOx surface passivation, which is expected to reduce the dark current of a Ge PD by 1 order of magnitude compared with conventional SiO2 surface passivation [29]. Since strong optical confinement can be achieved in the Ge layer on the GeOI wafer, the PD length necessary for NIR light absorption is approximately 10 μm. For a shorter PD length, the dark current can potentially be reduced to only a few nA. From the I-V curve, an on-off ratio of more than five orders of magnitude is also achieved, indicating a good junction property. This good junction property is also helpful for realizing high-performance active devices using lateral p-i-n junctions including Ge lasers, EA modulators, and PDs.
To evaluate the optical properties of the Ge rib waveguide PD, its photoresponsivity is measured. By cleaving the Ge rib waveguide PD in the middle, NIR light can be directly coupled into the cleaved end of the PD by using a lensed fiber. Figure 8 shows the wavelength dependence of the photoresponsivity in a cleaved Ge rib waveguide PD with a PD length of approximately 50 μm. The inset of Fig. 8 shows a microscope plan-view image of the evaluated Ge PD.
Fig. 8 Wavelength dependence of photoresponsivity in a 50-μm-long cleaved Ge rib waveguide PD. The inset shows an image of NIR light coupled into the Ge PD.
The fabricated Ge rib waveguide PD exhibits an extrinsic photo-responsivity of over 0.2 A/W with light input at a wavelength of 1550 nm. A relatively high photoresponsivity is also observed at wavelengths around 1600 nm, which may be due to the relatively long PD length and tensile strain inside the Ge layer on the GeOI wafer. Note that the physical origin of the tensile strain is attributable to thermal stress induced during a cooling down procedure after a thermal annealing process conducted during the GeOI wafer fabrication [20]. By taking into account the coupling efficiency between the lensed fiber and the Ge waveguide of 6.5 dB [30], an intrinsic responsivity of approximately 1 A/W is estimated for the fabricated device. Thus, low-dark-current operation and high photoresponsivity have been successfully achieved in a Ge PD fabricated on a GeOI wafer.
4. Integration of a-Si waveguide and Ge PD
On the basis of the above results, monolithic integration between an a-Si passive waveguide and a Ge PD is realized on a GeOI wafer. Figure 9 illustrates the process flow for Ge/a-Si integration.
A 50-nm-thick SiO2 layer is first deposited on a Ge surface by PECVD to serve as a hard mask, which is used to protect the Ge surface and define the Ge region for PD fabrication. After dry etching to form the Ge mesa, a GeOI substrate containing the SiO2 hard mask on top of the Ge layer is placed in a diluted sulfuric peroxide mixture (SPM) solution consisting of H2SO4:H2O2:H2O = 1:1:30 for 2 min to tilt the sidewall of the Ge mesa. This wet etching process is important for the uniform deposition of a-Si on the sidewall of the Ge mesa. After the removal of the SiO2 hard mask by BHF etching, the continuous deposition of a 30-nm-thick SiO2 interlayer followed by an a-Si layer is conducted by PECVD at 250 °C. Since the process temperature of a-Si deposition is much lower than the annealing temperature (550 °C) conducted during the GeOI wafer fabrication, we consider that the degradation on the Ge crystal quality during the integration is negligible, in conjunction with the SiO2 capping layer. This SiO2 interlayer enhances the adhesiveness between the Ge and the a-Si layer. By performing cross-sectional scanning electron microscope (SEM) observation, the conformal deposition of the a-Si layer on the Ge mesa is confirmed, as shown in Fig. 10.
From the SEM image, an angle of approximately 60° is observed on the tilted Ge sidewall. This tilted sidewall is helpful for reducing the reflection at the interface between the Ge device and the a-Si waveguide. By performing a 3D finite-difference time domain (FDTD) simulation for the case of butt-coupling between the a-Si waveguide and Ge mesa using Lumerical software, a reduction in the amount of reflected light of approximately 30% (−1.53 dB) is obtained by introducing a 60°-tilted Ge sidewall compared with that of a vertical Ge sidewall structure. After integrating the a-Si layer with the Ge mesa, an a-Si passive waveguide is defined by EB lithography and ICP dry etching. Grating couplers are not included here in order to investigate the wavelength dependence of the a-Si-waveguide-integrated Ge PD. Then, a lateral junction is formed on the Ge mesa, and GeOx passivation and SiO2 capping are conducted by similar processes to those explained previously. Finally, via holes and Ni contacts are formed. Figure 11 shows a top-view microscope image of the fabricated Ge PD monolithically integrated with an a-Si passive waveguide on the GeOI wafer, and the inset illustrates a 3D schematic of the device.
Fig. 11 Plan-view microscope image of a-Si-waveguide-integrated Ge PD. The inset illustrates a 3D schematic of the fabricated device.
By coupling an NIR light source to the cleaved edge of the a-Si waveguide through a lensed fiber, the properties of the fabricated Ge PD are studied. Figure 12(a) shows typical I-V curves of a 20-μm-long Ge PD integrated with a-Si waveguide without and with 0 dBm light input at a wavelength of 1550 nm.
Fig. 12 (a) Typical I-V curves of a 20-μm-long Ge PD integrated with an a-Si waveguide without and with 0 dBm light input at a wavelength of 1550 nm and (b) wavelength dependence of intrinsic responsivity of the Ge PD.
From the I-V curves, dark currents of 49 nA and 165 nA are observed in the a-Si-waveguide-integrated Ge PD under biases of −1 V and −2 V, respectively. Compared with the previous results for the Ge rib waveguide PD, a-Si-waveguide-integrated PD exhibits a larger dark current despite the GeOx surface passivation. This increased dark current may be caused by degradation of the Ge surface condition during the a-Si integration process, which should be further optimized in the future. Meanwhile, the design of the device structure of the integrated Ge PD should also be improved to achieve better performance. By coupling 0 dBm light at a wavelength of 1550 nm from a tunable laser into the cleaved edge of the a-Si waveguide through a lensed fiber, a photocurrent of approximately 70 μA is obtained in the integrated Ge PD. Assuming the coupling loss between the lensed fiber and a-Si waveguide to be 6.5 dB [30], an intrinsic photoresponsivity of over 0.2 A/W is obtained around 1550 nm. The obtained wavelength dependence of the photoresponsivity of the fabricated Ge PD is shown in Fig. 12(b). Currently, the photoresponsivity of the a-Si-waveguide-integrated Ge PD is low owing to the primitive integration scheme. To achieve a higher photoresponsivity, the lateral junction formation on the Ge mesa has to be optimized (i.e. optimal dopant activation process and junction location design). In addition, by introducing a proper Ge rib waveguide PD structure underneath the a-Si waveguide, the photoresponsivity of the Ge PD is also expected to be improved. Furthermore, by performing CMP on a-Si to achieve planar integration between the a-Si waveguide and the Ge PD, the photoresponsivity is expected to be increased significantly. Nevertheless, monolithic integration between an a-Si passive waveguide and a Ge PD on a GeOI substrate has been successfully realized.
5. Conclusion
We have carried out a proof-of-concept demonstration of a Ge/a-Si hybrid PIC platform using a wafer-bonded GeOI substrate. Taking advantage of the high crystal quality and the strong optical confinement in the Ge layer, a Ge rib waveguide PD with a low dark current and high responsivity is achieved on the GeOI substrate. We have also studied the capability of the a-Si waveguide of replacing a conventional Si waveguide for passive interconnection on a GeOI wafer. The fabricated a-Si strip waveguide exhibits a good transmission property compared with that of a conventional Si waveguide, suggesting the strong potential of applying a-Si for integrated optics on a GeOI wafer. By introducing a tilted sidewall structure in a Ge mesa, the conformal deposition of an a-Si layer is achieved for Ge/a-Si integration on a GeOI wafer, on the basis of which we have successfully realized an a-Si-waveguide-integrated Ge PD. Furthermore, the presented integration scheme is also applicable to III-V layers bonded on a SiO2/Si wafer [31,32], enabling greater functionalities and more possibilities. Thus, a promising Ge/III-V/a-Si PIC platform can be developed for advanced integrated photonics in the future.
Funding
New Energy and Industrial Technology Development Organization (NEDO); Japan Society for the Promotion of Science (JSPS) KAKENHI (JP26220605).
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