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Abstract
A dry etching process to transfer the pattern of a photonic integrated circuit design for high-speed laser communications is described. The laser stack under consideration is a 3.2-µm-thick InGaAs/InAlAs/InAlGaAs epitaxial structure grown by molecular beam epitaxy. The etching was performed using Cl2-based inductively-coupled-plasma and reactive-ion-etching (ICP-RIE) reactors. Four different recipes are presented in two similar ICP-RIE reactors, with special attention paid to the etched features formed with various hard mask compositions, in-situ passivations, and process temperatures. The results indicate that it is possible to produce high-aspect-ratio features with sub-micron separation on this multilayer structure. Additionally, the results of the etching highlight the tradeoffs involved with the corresponding recipes.
© 2024 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement
1. Introduction
The development of photonic integrated circuits (PICs) has been dominated by InP-based platforms because of significant achievements in realizing relatively complex structures [1]. The various applications of PICs include optical communications, microwave photonics, free space laser communications, 3D mapping light detection and ranging (LIDAR), and remote gas sensing [2,3]. PICs for coherent optical links may utilize light sources, photodetectors, modulators, and waveguides that are monolithically integrated. Generally, monolithic PICs offer reduced size, weight, parasitic capacitance, and cost, as well as enhanced stability, bandwidth, and power efficiency [2–4]. In this vein, InP-based monolithic photonic integration is extensively utilized to achieve photonic functionalities that include active components, such as high-efficiency quantum well lasers and modulators, optical amplifiers, and detectors [5]. Such a device may have a central quantum well active region in between top and bottom claddings, all grown epitaxially on InP [6]. In this design, it is vital that the desired components along with their corresponding shapes and dimensions are accurately transferred through the lithography process to patterns on the underlying substrate [7]. Our PIC design is based on a strongly injection-locked microring laser for ultrafast modulation, where efficient light coupling from the master laser into the microring laser structure is vital for proper operation [8]. The fabrication of this device requires dry etching to produce deeply etched high-aspect-ratio (HAR) ridge-waveguide lasers, photodetectors, injecting waveguide that maximize the injection coupling rate, and evanescently coupled output waveguides with sub-micron separation.
Distortions in the lithographically defined pattern during this transfer process can result in extrinsic losses, with light scattering causing conversion into radiation and reflected modes, and thus deteriorating the performance of any micro or nanophotonic device [9]. The integrated photonic structures must therefore be defined by etching that results in minimal pattern distortion. For good confinement in curved waveguides with small bending radius, the etching must be deep enough to selectively remove the entire top cladding, active region, and most of the bottom cladding. On the other hand, the design for single transverse mode operation for edge-emitting integrated photonic devices makes it mandatory for them to be thin and narrow [10]. Consequently, fabrication of a monolithic PIC with narrow structures and deep sidewalls requires high-aspect-ratio (HAR) etching to produce the desired components. Inductively-coupled-plasma reactive-ion etching (ICP-RIE) is a proven method to produce anisotropic etched features on GaAs [11] and InP [12].
The ICP-RIE plasma etching utilizes a high-density plasma of reactive species to produce low-damage rapidly etched features. This technique conveniently allows independent control of plasma density and ion energy. The ICP power is responsible for the plasma density, while the RF power is used to decouple the reactive species from the plasma and drive them towards the sample surface [13,14]. The reactive species originated in the plasma are responsible for the chemical etching of the material. However, the chemical etching mechanism produces isotropic profiles [15]. Therefore, a physical etching mechanism must be introduced to the etching process to counter the isotropy and produce reasonably vertical sidewalls. A suitable mask must also be employed that can be critical to the final sidewall profile [16]. At the same time, introducing an in-situ sidewall passivation mechanism is important to minimize undercutting and to produce relatively smooth sidewall morphology [15]. To summarize, the following factors are considered to produce an acceptable etching using ICP-RIE: a) balance between physical and chemical etching mechanisms, b) appropriate masking material, and c) engineering the formation of an in-situ passivation layer on the sidewalls of the profile. As an example, HAR features on InAlGaAs/InP were produced by Guilet et al. using a triple spiral antenna ICP system that could support low process pressures of 0.5 to 1 mTorr [17]. Such low process pressures, however, are difficult to achieve in common ICP-RIE systems [12]. Moreover, the etched structures were stand-alone stripes, not coupled structures with critical separation distance. In this vein, HAR GaAs features were fabricated using a time multiplexed ICP etching tool by Golka et al. [18]. Unlike conventional ICP-RIE systems, the time-multiplexed method uses a complex three-step process to perform the etching and also produces periodic vertical scallop-like structures on the sidewall [7]. Nano waveguide features with HAR etching of GaAs and GaAs/AlGaAs were reported by Volatier et al., using a conventional ICP-RIE system [7]. However, their material system did not have any indium-containing tertiary or quaternary materials, as is the case in this paper (see Section 2). InGaAs nanowires were fabricated by ICP-RIE using a complex multi-cycle recipe, but the structures did not have any narrow areas between the nanowires [19]. Docter et al. developed an ICP-RIE etching method to produce HAR features on InGaAsP/InP multilayer structure that did not include any Al-containing quaternary materials [20].
Comparison of the different methods of ICP-RIE etching for heterojunction-based devices involving InGaAs-based materials made it clear that the structure under consideration here, designed for an integrated ultrahigh-speed injection-locked ring laser, required development and optimization of dedicated etching recipes. Therefore, in this work we report the etching of an InGaAs/InAlAs/InAlGaAs structure producing monolithic HAR features with sub-micron separation using single-step recipes that were run on conventional ICP-RIE systems. We experimented with four different recipes with two different hard-mask material compositions.
2. Materials and method
The multilayer structure for the PIC under consideration is shown in Fig. 1. It was designed to be lattice-matched to InP and was grown on n-doped epi-ready InP using phosphorus-free MBE. The structure was designed to emit at 1.55 µm, with claddings designed not only to provide light confinement but also to facilitate current injection aided by dopants. The bottom cladding consisted of a Si-doped (concentration of 1018/cm3) 1.4-µm-thick In0.52Al0.48As material. The active region consisted of 7 8-nm-thick In0.53Ga0.47As quantum wells (QWs) as the gain medium, separated by 8-nm-thick In0.53Al0.2Ga0.27As barriers. Two 250-nm-thick In0.53Al0.2Ga0.27As undoped spacer layers were placed on either side of the active region for reduced penetration of the optical mode into the claddings and, therefore, reduced free-carrier absorption. The top cladding consisted of a Be-doped (concentration of 2 × 1018/cm3) 1.4-µm-thick In0.52Al0.48As material. The structure was capped with a 100-nm-thick highly Be-doped (concentration of 2 × 1019/cm3) layer for formation of an ohmic contact with Ti/Pt/Au metallization. The realization of our PIC necessitated a deeply etched monolithic pattern that included the following device components: a whistle-geometry microring laser (WRL) [8], an injecting waveguide, an edge-emitting distributed-Bragg-reflector (DBR) master laser, an integrated whistle-geometry microring photodetector, and an outcoupling waveguide evanescently coupled to the WRL. A schematic outline (not to scale) of these components is shown in Fig. 2.
The overall fabrication process flow used to perform the etching experiments is presented in Fig. 3. The electron beam (e-beam) lithography was performed on the as-grown sample illustrated in Fig. 1, resulting in a written pattern of the PIC design on the surface (Figs. 3(a) and 3(b)). A hard mask emulating the same design was then created on the sample surface using e-beam evaporation followed by a lift-off procedure (Fig. 3(c)). The sample was then dry-etched using Cl2-based chemistry to transfer the pattern permanently on the substrate (Fig. 3(d)).
Fig. 3. An illustration of the overall process flow showing (a) sample coated with e-beam resist; (b) DBR and ring photodetector portion of a pattern written after e-beam exposure and development; (c) creation of the tri-metal hard mask after e-beam metal deposition and lift-off; and (d) transfer of the pattern onto the substrate using ICP-RIE plasma etching.
2.1 Mask fabrication
The first step was to perform e-beam lithography on a cleaned 1 cm × 1 cm sample using a bilayer polymethyl methacrylate (PMMA) e-beam resist for creating an effective negative sidewall for lift-off [21]. To accommodate an e-beam-evaporated tri-metal mask with a thickness of up to 300 nm, we implemented a bilayer PMMA resist combination of 495 A6 and 950 A7. The PMMA 495 A6 resist was spin-coated on the sample at 2000rpm, followed by a soft bake procedure at 180 °C for 2 minutes. The same procedure was then repeated for the PMMA 950 A7. A JEOL JBX-6300FS 100-kV e-beam lithography system was then used to expose the sample at 800 µC/cm2. The sample was then developed using a 1:3 mixture of methyl isobutyl ketone (MIBK) to isopropyl alcohol (IPA) for 1 minute and 45 seconds, followed by a 10 to 15 seconds IPA rinse, and immediately dried using a N2 blow gun. The sample was then descummed using an Anatech Barrel Asher by exposing it to a 100-W O2 plasma for 2 minutes. The sample was then dipped in buffered oxide etch (BOE) for 1 minute to remove any native oxide. Immediately, the sample was loaded into a Temescal e-beam evaporator system and the pump-down process was initiated. When the base pressure of the system reached 2 × 10−6 torr, the Ti, Au, and Cr of thicknesses 20/100/130 nm were deposited. The choice of Ti. Au, and Cr was dictated by requirements of good adhesion to the semiconductor surface (Ti), good electrical conductivity (Au), and slow etch rate (Cr). After retrieving the sample from the e-beam evaporator, it was soaked in Microchem Remover PG for 8 hours, after which a lift-off procedure was performed. Figure 4 shows scanning electron microscopy (SEM) images of the patterned tri-metal mask after the lift-off procedure. Alternatively, a slightly different method was followed for creating a Si3N4/Cr mask instead. For the baseline process of Volatier et al. [7], a Trion Orion III plasma-enhanced chemical vapor deposition (PECVD) system was used to deposit 1 µm of Si3N4 on a cleaned 1 cm × 1 cm sample. E-beam lithography and development were then performed, followed by e-beam evaporation and lift-off of 50 nm of Cr. The Cr-capped Si3N4 was then patterned by etching in a CF4/Ar/O2 ICP-RIE plasma. The same instrumentation was used for all etching recipes reported in this paper.
Fig. 4. SEM imaging of the patterned Ti/Au/Cr tri-metal hard mask before the dry etching, showing (a) the entire device; (b) the WRL structure with the outcoupling waveguide with a larger magnification view of the gap between the ring and the outcoupler in the inset; and (c) rear DBR section of the master laser, facing the monitoring ring photodetector.
2.2 Etching process
We have developed four different etching recipes for a dual-chamber PlasmaTherm Apex SLR ICP system, with progressively better etching results. We refer to two chambers as ICP1 and ICP2, respectively. The chlorine chamber ICP1 had Cl2, BCl3, N2, Ar, and O2 as the available process gases, while CF4, SF6, Cl2, H2, Ar, and O2 were the available process gases in the fluorine chamber ICP2. ICP1 had a platen temperature range from 20 °C to 200 °C and ICP2 had a platen temperature range from 20 °C to 190 °C. Both chambers had a maximum ICP power of 1 kW at 2 MHz and a maximum RIE power of 600 W at 13.5 MHz. Both chambers used a mechanical clamp with adjustable He backside cooling and an isolated load lock compartment.
The PlasmaTherm Apex ICP-RIE reactor system was initially conditioned by running an O2 cleaning recipe for 20 minutes, followed by a 5-minute run of the actual recipe. Next, the samples with the deposited hard mask were loaded into the load-lock chamber on a 4-inch Si wafer with no thermal grease. After transferring the sample and the carrier to the process chamber, an appropriate Cl2-based dry etching recipe was run.
After etching, the sample was characterized using top-down and slanted SEM imaging, optical microscopy, and profilometry. The SEM imaging was performed to qualitatively assess the results of the etching process. In addition, the thickness of the remnant mask, distance between the etched features, and width of the waveguide structures were also measured using SEM. Alpha-stepper profilometry was used to measure the depth of the etched features and was verified with the slanted SEM imaging. Optimization of etching procedures was an exhaustive process, given the inconsistencies of reactor conditions between etches in a multi-user facility, variable mask depletion rates across recipes, and utilization of various hard mask compositions.
2.3 Recipe development
As an overview, our study started with the baseline recipe of Volatier et al. [7]. We then optimized this baseline recipe in terms of the process pressure and the process temperature, and we also experimented with the hard mask composition. The results of this experimentation provided insight for us to not only choose a resilient hard mask, but also to implement and optimize three more etch recipes. In these three recipes, we optimized the process pressure, process temperature, and additive gases to produce the best possible results in the ICP/RIE reactors that were at our disposal.
The starting point for the series of etching experiments involved the baseline Recipe 1. It was based on the process of Volatier et al. [7], where N2 was used as an additive gas to Cl2/BCl3/Ar plasma for producing HAR etching of GaAs/AlGaAs. The same authors also stated that addition of 10-13% of N2 to the total volumetric gas flow can promote optimal passivation of the sidewalls. We first experimented with this recipe on samples with a Si3N4/Cr hard mask at process pressures of 7 and 5 mTorr, respectively. Recipe 2 was an optimized version of the baseline recipe. The optimization to this process included a higher RIE power, lower volumetric gas flows for Ar and N2, and a higher process temperature. Additionally, a tri-metal hard mask was employed on the samples that were etched using Recipe 2. Our third recipe was based on the paper of Parker et al. [12], where a recipe based on Cl2/H2/Ar plasma to produce near vertical feature by etching InP/InGaAsP was reported. Our last recipe employed N2 as a passivation gas rather than H2, and the etching was performed at an elevated temperature of 200 °C. Recipes 1, 2, and 4 were used in ICP1, while Recipe 3 was used in ICP2.
During the preliminary runs of Recipes 3 and 4, it was realized that the PlasmaTherm Apex ICP reactors failed to sustain a plasma at a process pressure of 1.5 mTorr with their corresponding gas flow ratios. Therefore, a two-step tuning method was employed. The appropriate gases were introduced to the process chamber and the plasma was ignited at a higher pressure of 5 mTorr. The ICP ‘Load’ and ‘Tune’ parameters, responsible for the impedance matching, were continuously tuned until a stable plasma with zero reflected power was achieved and the values of the two parameters were recorded. While the recipe was still running, the process pressure was changed to 1.5 mTorr and while the plasma was sustained, the same process described above was repeated. The second set of ‘Load’ and ‘Tune’ parameters was recorded and then used in the actual recipe. Finally, we ignited the plasma at 5 mTorr with the second set of tuning parameters and changed the process pressure immediately to 1.5 mTorr to have a stable and sustained plasma.
3. Results
3.1 Recipe 1
The first batch of samples that were used for etching according to Recipe 1 had a bilayer Si3N4/Cr mask of thicknesses 1 µm and 50 nm, respectively. The SEM images of the etched WRL structure after using Recipe 1 with substrate temperature of 20 °C are shown in Figs. 5(a) and 5(b). The etch depth was measured to be ∼2.1 µm, with an aspect ratio of 0.91. Despite having a very smooth sidewall, manifestation of profile distortion in the form of excess tapering was evident. We believe that this profile distortion occurred due to the following reasons: deflection of the reactive ions from the plasma due to charging of the sidewall, excessive sidewall passivation, and high process pressure. Ishchuk et al. reported that HAR structures can suffer profile distortions such as notching, bowing, and trenching resulting from deflection of the energetic ions from the plasma due to charge buildup on the sidewall [22][23]. Volatier et al. [7] reported on N2-assisted formation of a polymer that passivates the sidewall during Cl2-based dry etching of GaAs/AlGaAs using the same chemistry. The 1-µm thickness of Si3N4 in the mask and the presence of a passivating polymer in the sidewall could have certainly contributed to the charging-induced ion deflection. On the other hand, higher process pressures are known to adversely affect the verticality of the sidewall [12].
Fig. 5. The results of etching a sample using Recipe 1 with a bilayer Si3N4/Cr mask: (a) top-down SEM image of the microring and outcoupler section; this sample used a 1 µm/50 nm bilayer Si3N4/Cr mask and a process pressure of 7 mTorr; (b) slanted SEM image of the same sample as shown in (a); (c) top-down SEM image of the microring and outcoupler section; this sample used a 300 nm/50 nm bilayer Si3N4/Cr mask and a process pressure of 5 mTorr; and (d) slanted SEM image of the same sample as shown in (c).
As a measure to reduce these artifacts, in subsequent etching experiments we changed the mask thicknesses on the samples, reduced the process pressure to 5 mTorr, and increased the process temperature to 100 °C. The new Si3N4 and Cr bilayer hard mask was 300 nm and 50 nm thick, respectively. The result of the etching is shown in Figs. 5(c) and 5(d). An enhanced etch depth of 2.7 µm with an aspect ratio of 2.9 was recorded. The increased process temperature and lower process pressure resulted in enhanced etch rate of 12 nm/s, compared to 9.3 nm/s for the earlier version of Recipe 1. The significantly thinner Si3N4 layer led to less local charging and decreased deflection of the plasma-generated ions. However, this etching recipe did not produce any acceptable separation between closely located structures. Despite producing relatively smooth sidewall surface, we believe that the N2 volumetric flow rate was too high in this case. This resulted in an excess sidewall passivation, which in turn produced an exaggerated tapering of the wall that made it impossible to create sub-micron gaps between the structures.
The top-down SEM images of Figs. 5(a) and 5(c) may be interpreted as indicating a severe case of lateral etching of the mask. However, this was not the case as the waveguide width in our design was very close to the top width of the etched features. Both Recipe 1 experiments used a Cr-capped mask with a significantly thicker layer of Si3N4 underneath, deposited by PECVD. As reported in [24], the Ar ion milling rate of e-beam evaporated Cr is significantly higher than that of Si3N4. Therefore, the Cr mask could have a narrower width than that of the Si3N4 mask underneath after the etching. The now exposed Si3N4 mask would not be easily distinguishable in SEM, as it would have a very similar contrast to that of the polymerized sidewall. A closer examination of the outcoupler section of the slanted image shown in Fig. 5(d) indicates a slightly lighter band on the etched waveguide topped with a narrower and darker band. With reduced severity of the sidewall erosion of the entire thickness of the mask, the exaggerated sloping of the sidewall most likely is a manifestation of ion deflection and excessive sidewall passivation.
3.2 Recipe 2
The results of Section 3.1 led to implementation of the second recipe listed in Table 1, with a 25% increase in RF power and 5% decrease in Ar and N2 volumetric flow rates. In addition, we utilized a tri-metal hard mask consisting of Ti/Au/Cr of thicknesses 20/100/130 nm, respectively. Figure 6 shows the SEM images of the resulting etched structures. A profile depth of 2.4 µm with a maximum aspect ratio of 1.6 was recorded, with an enhanced etch rate of 26.6 nm/s. The minimum aspect ratio was 1.2 with 66 nm of the mask remaining after the etching, suggesting a selectivity of 13:1. The use of this recipe resulted in preservation of the feature to a higher depth, indicating a better etch directionality. This improved directionality was achieved due to a higher RF power and an all-metal mask that reduced charging effect and increased the etch selectivity. From this point forward with our etching experiments, we adopted the tri-metal hard mask to be the standard mask material. However, the higher RF power and lower process pressure negatively contributed by causing micro masking. With V-shaped separations between the structures (Fig. 6(b)) to a depth of 280 nm, the separation depth was far from adequate.
Fig. 6. Slanted SEM images of a sample that was etched using Recipe 2 with a tri-metal mask that show: (a) the microring, the outcoupler, and part of the injecting waveguide, with a larger magnification image of the microring and the outcoupler in the inset; (b) the gap between the DBR laser and the injecting waveguide, with a larger magnification image of the gap in the inset; and (c) the back side of the DBR laser, rear DBR mirror, and a photodetector, with a larger magnification image of the DBR mirror and part of the photodetector shown in the inset.
Table 1. Recipes developed for the PlasmaTherm Apex ICP-RIE systema
3.3 Recipe 3
At this juncture, it became evident that the main challenge was to achieve enhanced aspect ratio features along with deeper vertical separation between the structures. Therefore, Recipe 3 was implemented in the ICP2 reactor, with the process pressure and temperature of 1.5 mTorr and 190 °C, respectively. Figure 7 depicts the etched structure obtained using this recipe. An etch depth of 3.2 µm was recorded, with a maximum aspect ratio of 8.8 and a minimum of 2.75 observed. A 297-nm-wide gap between the microring and the outcoupling waveguide was produced (Fig. 7(a)). The structures were ∼370-nm wide with ∼550-nm separation up to a depth of 2.55 µm in the DBR region, as shown in Fig. 7(c). The narrowest separation observed was ∼115 nm that eventually diminished when it reached a depth of ∼1 µm. Approximately 135 nm (54%) of the metal mask remained after the etching, indicating an etch selectivity of 28:1.
Fig. 7. Slanted SEM images of a sample that was etched using Recipe 3 with a tri-metal mask that show (a) the ring, the outcoupler and part of the injecting waveguide, with a larger magnification image of the ring and the outcoupler in the inset; (b) the gap between the DBR laser and the injecting waveguide, with a larger magnification image of the gap in the inset; and (c) the side of the DBR laser with the rear DBR mirror and a ring photodetector, with a larger magnification image of the DBR mirror and part of the photodetector shown in the inset
A lower process pressure of 1.5 mTorr increased the mean free path of the ions and resulted in improved anisotropy, as suggested by Parker et al. during their InP/InGaAsP etching experiments [12]. A high process temperature of 190 °C enabled the sublimation of etch byproducts from the walls and from the gaps between structures. Finally, H2-assisted in-situ passivation helped maintain a relatively smooth sidewall. Sidewall roughness was found to be sub-100 nm, which was caused by lateral erosion of the mask.
3.4 Recipe 4
The highest temperature that could be reached in ICP2 was 190 °C. We further wanted to experiment with running a similar recipe in ICP1 that was capable of a 200 °C processing temperature that would further increase the volatility of the etching byproducts [19]. However, in ICP1, we had to use N2 as the additive gas instead of H2. Eventually, after a series of optimization runs on InP samples, Recipe 4 from Table 1 was created. Figure 8 shows the SEM images depicting the etched features on our multilayer structure after using this recipe. A very high aspect ratio of 11.37 was recorded in the DBR region (Fig. 8(c)). The aspect ratio on the waveguide sections was 2.28. Figure 8(b) reveals a separation of ∼429 nm achieved in the gap, narrowing down to 400 nm to a depth of 3 µm. Approximately 74 nm of the mask remained after the etching, indicating a selectivity of 17:1 in material-to-mask etch ratio. The results indicate some isotropic etching in the features, which is a result of a chemically dominant aggressive etching process. This isotropy caused exaggerated undercuts in the DBR region that compromised the structural integrity of the etched features. The sidewall roughness was noticeably higher as well. We believe this was due to the lack of in-situ passivation. A lower etch selectivity also indicates a hyperactive Ar milling process. More importantly, these results corroborate with the earlier claims [12] of the presence of in-situ N2 and H2-promoted passivation in BCl3/Cl2/Ar/N2 and Cl2/H2/Ar chemistries, respectively.
Fig. 8. Slanted SEM images of a sample that was etched using Recipe 4 with a tri-metal mask that show: (a) the microring, the outcoupler, and part of the injecting waveguide, with a larger magnification image of the microring and the outcoupler shown in the inset; (b) the gap between the DBR laser and the injecting waveguide; and (c) the side of the DBR laser with the rear DBR mirror and a microring photodetector, with a larger magnification image of the DBR mirror and part of the photodetector shown in the inset.
4. Discussion
The development of a single-step etching recipe for an epitaxial stack comprising multiple materials can be challenging [16]. The etch chemistry must produce acceptable sidewall quality for all the materials present in the stack. In addition, the vertical directionality of the etching process must be maintained to reach the desired profile depth. This objective can be achieved by considering the following factors: a) establishing a balance between chemical and physical etching mechanisms; b) using in-situ sidewall passivation; c) using higher process temperatures; and d) selecting a hard mask that can sustain the etching duration [7][12][25].
We used Ar in all our etching recipes not only to facilitate physical milling, but also to stabilize the plasma. Our experiments indicated that the dominance of the chemical mechanism can cause isotropic etching. Conversely, we found that excess physical milling could cause depletion of the hard mask, resulting in profile distortion and exaggerated micro masking. Such was the case in the etching process that used Recipe 2.
In-situ sidewall passivation is typically engineered by the formation of a polymer film by the etching gases, and the process can be assisted by using an additive gas [25]. The polymer film coating the sidewalls not only provides anisotropy by avoiding lateral etching, but also minimizes roughness [26]. While results from Recipes 1 and 2 showed the effect of excess passivation, Recipe 4 demonstrated that insufficient passivation could result in isotropic etching with enhanced sidewall roughness. Recipe 3 exhibited the result of a balanced H2-assisted passivation. Furthermore, a comparison with Recipe 3 (Fig. 7) illustrates the excess passivation in the case of Recipe 2 (Fig. 6). Especially significant are the results showing the gap between the DBR laser and the injecting waveguide, as well as the side views of the DBR mirror. In contrast to Figs. 7(b) and 7(c), Figs. 6(b) and 6(c) show material buildup in the tight regions restricting the etching.
Substrate temperatures higher than 150 °C are reported to increase the volatility of InClx etching byproducts [12]. At the time when experiments with Recipes 1 and 2 were performed, the substrate temperature that ICP1 could support was only 100 °C. Consequently, Recipe 2 had a process temperature of 100 °C but a high Ar content, which contributed to a higher physical etching rate and increased milling of the mask. In contrast, Recipe 4 had a significantly higher process temperature of 200 °C with significantly lower Ar flow rate, which produced sub-micron separation up to a depth of 3 µm. Out of the four recipes, this recipe achieved the best separation. This happened most likely because the sufficient sublimation minimized the redeposition of the etching byproducts and thus maintained the gaps between the structures.
Lastly, the etching within the HAR gaps between the structures was difficult due to the RIE loading effect [26]. A balance between increased RIE power and lower process pressure has been reported to minimize the RIE loading effect [27]. Our experiments suggested that this effect cannot be eliminated, but it can be reduced to produce acceptable gaps between narrow structures. The PlasmaTherm Apex SLR ICP reactors that we used could not support a process pressure lower than 1.5 mTorr. Therefore, it would be worthwhile to repeat these experiments at process pressures lower than 1.5 mTorr. We believe such efforts would pay dividends in terms of improved separation between structures. As an example, for an ultrahigh-speed -aser-based PIC, such as ours, preservation of the designed gap between the devices would provide the necessary level of light injection for ultrafast operation of the PIC [8]. However, the recipes would have to be optimized for the lower process pressure. More importantly, our experience with the etching experiments revealed that the etching conditions even between similar reactors can be quite different. Therefore, emulating a previously reported etching recipe requires thorough optimization.
5. Conclusions
It was shown in this work that monolithic HAR PIC structures with sub-micron separation can be fabricated on InGaAs/InAlAs/InAlGaAs structure using conventional ICP-RIE systems. The results of using four competing recipes were presented to emphasize the importance of in-situ sidewall passivation, mask composition, process pressure, and substrate temperature on etching results. This is important for the development of dry etching recipes for fabrication of monolithic PICs that include light sources, photodetectors, modulators, and waveguides on InP-based material systems. The recipe with the Cl2/H2/Ar chemistry produced the best overall result in terms of aspect ratio, sidewall roughness, mask integrity, and separation between structures.
Funding
Office of Naval Research (N00014-17-1-2416, N00014-21-1-2683).
Acknowledgements
This work was performed, in part, at the Center for Integrated Nanotechnologies (CINT), an Office of Science User Facility operated for the U.S. Department of Energy (DOE) Office of Science. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International, Inc., for the U.S. DOE’s National Nuclear Security Administration under contract DE-NA-0003525. The views expressed in this paper do not necessarily represent the views of the U.S. DOE or the United States Government. The CINT portion of the work was done under user projects 2017BU077, 2019BU0171, 2021BU0191, and 2023AC0221.
The authors would like to thank Stephen Wawrzyniec and Douglas Wozniak for their valuable contributions and suggestions towards making the ICP-RIE reactors ready and available for the etching experiments at the Center for High Technology Materials at the University of New Mexico.
Disclosures
The authors declare no conflicts of interest.
Data availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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