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Abstract
In the realm of advanced computing and signal processing, the need for optimized data processing methodologies is steadily increasing. With the world producing vast quantities of data, computing architectures necessitate to be swifter and more energy efficient. Edge computing architectures such as the NetCast architecture [1] combine the strength of electronic and photonic computing by outsourcing multiply-accumulate operations (MAC) to the optical domain. Herein we demonstrate a hybrid architecture, combining the advantages of FPGA data processing facilitating an ultra-low power electro-optical “smart transceiver” comprised of a lithium-niobate on insulator photonic circuit. The as-demonstrated device combines potential GHz speed data processing, with a power consumption in the order of 6.63 fJ per bit. Our device provides a blueprint of a unit cell for a TFLN smart transceiver alongside a variety of optical computing architectures, such as optical neural networks, as it provides a low power, reconfigurable memory unit.
© 2023 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement
1. Introduction
The relentless growth of data-intensive applications, compounded with the increasing demand for higher data rates and capacities, has put a significant strain on data communication networks [1,2]. Data centers, the backbone of information storage and processing, have experienced an array of challenges as a consequence of this expansion, most notably the massive power requirement necessary to sustain and cool large-scale data center systems [3,4]. Accordingly, research efforts are currently underway to improve beyond current technology.
By leveraging the unique properties of light, modern technology works towards outsourcing calculations and data streams from the electrical to the optical domain. Optical computing offers unparalleled advantages, including higher data throughput, reduced latency, and improved energy efficiency [1,5]. Moreover, such an architecture is uniquely suited for kernel-based CNN systems and to date has been successfully employed for Natural Language Processing [6,7], image detection [8], and computer vision applications [9]. Though these serve as examples of application specific accelerators, they suffer from major drawbacks like high propagation loss or low bandwidth. Due to its unique optical properties, thin film lithium niobate-on-insulator (TFLN) is a promising material platform to overcome those issues.
In this study, we investigate FPGA-controlled thin film lithium niobate-on-insulator (TFLN) electro-optic modulators (EOMs) as electro-optical “smart transceivers”. Smart-Transceivers merge the process of data transmission with multiply-accumulate-operations (MACs) as they outsource linear operations to the optical domain, hence eliminating memory access. Moreover, they in principle serve as blueprint cells for photonic integrated processors suitable for in-memory computing, as they provide a reconfigurable high-speed, low-energy memory unit.
EOMs implemented in the TFLN photonic platform rely on the Pockels effect, which is observed in non-centrosymmetric media as a response to an external electric field, leading to an almost instantaneous phase-shift in the waveguide. Such electro-optic modulation was demonstrated in nanophotonic lithium niobate waveguides with bandwidth exceeding 100 GHz accompanied by half-wave voltages in the single-digit range [10]. Birefringent lithium niobate is an exemplary candidate for such materials, as it possesses a strong Pockels coefficient of r33 ≈ 31 pm/V along the crystal C-axis [11]. Furthermore, it maintains a large transparency window that ranges from the ultra-violet ($\lambda$ ≈350 nm) to the infrared ($\lambda$ ≈5 µm) [11], thereby allowing the realization of waveguides featuring propagation loss of approximately 0.2 dB/cm [12] in single-mode operation and down to ≈ 2.7 dB/m in multi-mode waveguides operating the infrared wavelength range [13]. Additionally, lithium niobate exhibits excellent nonlinear optical properties, making it ideal for various nonlinear optical processes, including frequency doubling [14], parametric amplification [15], and optical parametric oscillation [16], which facilitate the generation of new wavelengths and nonlinear interactions. Here, we demonstrate how high-extinction ratio electro-optic modulators made from lithium niobate-on-insulator can be utilized towards outsourcing multiply accumulate operations from field-programmable gate arrays (FPGAs) to ultra-fast, energy-efficient photonic integrated circuits.
2. Setup
The utilization of TFLN photonic integrated circuits (PICs) is demonstrated in this work to showcase their potential in accelerating data processing by transferring it to the optical domain. This transfer process involves the mapping of digital bit values of a field-programmable gate array (FPGA) to their respective analog optical counterparts. The device presented in this study serves as a modulator that encodes bits via optical intensity mapping. A schematic of the PIC accelerated processor setup is depicted in Fig. 1. This setup can be divided into two separate sections, namely the system-on-chip (SoC) that functions as the electronic control unit and the PIC transceiver unit, primarily a TFLN electro-optic modulator (EOM). Between these two systems, analog data is exchanged in the electrical domain. The PIC is interfaced with an electrical probe (Infinity I40-A-GSG, FormFactor GmbH), while an AC-coupled fiber optic InGaAs photoreceiver (2117-FC-M, NewFocus) is employed to convert the optical signal back to the electrical domain. The PIC operates at a wavelength of 1550 nm, which is supplied by a tunable continuous-wave laser (TSL-770, Santec Corporation).
Fig. 1. Sketch of “smart transceiver” and control electronics. The setup may be bifurcated into two distinct segments. The System on Chip (SoC) is composed of a Random-Access Memory (RAM), which contains both the data to be processed and the received data. The Central Processing Unit (CPU) facilitates communication with the Field-Programmable Gate Array (FPGA) and RAM, with the objective of regulating the process. The FPGA is responsible for executing the convolution process, whereas a Digital-to-Analog Converter (DAC) and an Analog-to-Digital Converter (ADC) are employed to translate data into the analog domain to outsource operations to the TFLN PIC. The latter is connected to an electrical probe to transmit modulation voltages and is equipped with a continuous wave 1550 nm laser, which is readout by a photoreceiver. Together, the PIC and photoreceiver constitute the “smart transceiver”.
2.1. Fabrication of lithium niobate electro-optic modulators
To harness the Pockels effect in X-cut thin film lithium niobate, electro-optic modulators are standardly realized in the form of a Mach-Zehnder interferometer (MZI), where the two waveguide arms are patterned parallel to the Y-axis of the crystal and through coplanar electrodes in Ground-Signal-Ground (GSG) configuration, as depicted in Fig. 1. As such, there is an efficient overlap between the TE optical mode supported by the waveguide and the Z component of the external electric field via the highest element of the second-order susceptibility tensor. Importantly, as the electric fields applied across the two arms of the MZI exhibit opposite polarity, with the application of a single electrical signal, it is possible to induce a phase-advance on one arm and a phase-delay (of the same amount) on the other arm, thus enhancing the modulation efficiency of the device by a factor 2 when driven in the so-called “push-pull configuration”.
The manufacturing process commences with a plain 300 nm thick x-cut lithium niobate film, which is bonded on a 4.7 µm thick silicon dioxide layer, thermally grown on a silicon substrate (Fig. 2 (a)). The photonic die undergoes electron beam patterning lithography (EBPL) with spin-coated negative photoresist (ArN 7520, Allresist GmbH), as sketched in Fig. 2 (b), Consecutive inductively-coupled plasma reactive-ion etching (ICP-RIE), using an optimized Ar milling process transfers the resist pattern into the TFLN layer. The etched sample is then post-etched in RCA-1 to eliminate redeposition caused by the employed purely physical sputtering process, leaving TFLN waveguides (Fig. 2 (c)). Subsequently, annealing at 400°C is carried out to enhance the optical transmission of the patterned waveguides. An 800 nm thick buffer layer of hydrogen silsesquioxane (HSQ) is then spin-coated on the patterned lithium niobate film and cured with a blanket electron-beam exposure (Fig. 2(d)). This layer acts as a spacer between the etched TFLN and the coplanar waveguide (CPW), in order to mitigate the metal-induced absorption loss. Finally, the CPW, consisting of a 80 nm thin gold layer, is fabricated via standard physical vapor deposition (PVD) and lift-off processes (Fig. 2 (e)).
Fig. 2. PIC manufacturing flow. (a) The fabrication starts from a commercial 300 nm X-cut TFLN on 4.7um SiO2 on Si wafer. (b) The wafer is patterned using EBPL utilizing spin coated negative photoresist (ArN 7520). (c) The patterned photomask is transferred into the TFLN by highly directional ICP-RIE and subsequent wafer cleaning chemistry. (d) An 800 nm Thick layer of HSQ is coated and e-beam cured on top of the fabricated PIC for environmental protection and spacing of gold electrodes. (e) Electrodes are deposited via PVD and lift-off of on EBPL patterned photoresist (PMMA).
2.2. SoC programming and control electronics
The SoC combines a generic processing unit (CPU) with re-configurable programmable logic (FPGA). In data processing applications, the CPU can perform high-level tasks such as algorithm control while the FPGA can perform specific narrowly defined processing tasks as a so-called accelerator. The concept can be taken one level further by using a PIC as an analog MAC accelerator for the FPGA. High-speed DACs and ADCs serve as the interface between the digital FPGA domain and the analog PIC domain. The RFSoC ZCU216 evaluation board was used for this application, as it offers sixteen DAC and ADC channels which interface tightly with the programmable logic, with DDR memory that can be addressed via direct memory access (DMA) to drive the processor.
The DACs/ADCs on the ZCU216 SoC have differential outputs/inputs that are converted to single-ended using baluns with appropriate bandwidth. A relatively low-speed DAC (Linear Technology LTC2668-16) connected to the SoC via serial peripheral interface (SPI) is used to create the 5.5 V offset voltage, which serves as the operating point of the modulator. The DC offset and AC modulation voltages are combined using a bias-T with appropriate bandwidth. The modulated light is detected using the aforementioned photo-receiver utilizing the advantage of AC-coupling to prevent the inevitable bias current to limit the receiver gain due to the limited output swing range.
2.3. Device characterization
It is essential to perform a system-wide benchmark before conducting processing to evaluate the expected performance. To begin with, the electro optic modulator (EOM) of the photonic integrated circuit (PIC), of length of 1.7 mm and an electrode gap of 2 µm needs to be characterized. A triangular voltage signal of 20 Vpp was used to drive the EOM and measure its half-wave voltage V$_\pi$. The voltage-dependent output intensity is illustrated in Fig. 3, indicating a V$_\pi$ of about 10 V from the depicted sinusoidal fit. To achieve a linear optical response to electrical signals, the modulator must operate at 50% transmission, where the slope is the steepest and symmetric for both voltage polarities. To shift the modulator to the operating point, a DC-bias of 5.5 V was added to the modulation voltage. 14 bits could be encoded by the DAC output, with a voltage range of 1 Vpp after converting to a 50 Ω single-ended output, corresponding to an optical signal range of approximately 43.33% to 56.66% transmission as depicted by the purple and green lines in Fig. 3. The EOM was characterized and subsequently linked to the SoC in order to evaluate the overall signal-to-interference ratio including noise and distortion (SINAD) of the system. The slowest clock of the FPGA is set to2.5 MHz, which necessitates overclocking of the EOM. To mitigate DC-drifts, occurring for a sequence of bits encoded with the same voltage polarity, every sample is sent twice: once normal and once inverted (non-return-to-zero (NRZ)), as shown in Fig. 4(a). This modulation scheme, which corresponds to upsampling of the data points by a factor two and then mixing with half the sampling frequency, effectively cancels any DC components at the cost of reducing the effective sampling frequency by a factor two. Furthermore, due to overclocking, the rise time of the EOM is heavily reliant on the encoded value stored in the previous clock cycle. Therefore, every encoded pixel is cropped at half of its time bins and filled with signal-dead time (return-to-zero (RZ)), as shown in Fig. 4 (a). Thus, the dependence of the two following bits could be significantly reduced.
Fig. 3. EOM modulation response. A Half-wave voltage of V$_\pi$ = 10 V is measured. A DC-offset of 5.5 V shifts the transmission to the working point of the modulator, indicated by the dotted line. With an applied AC voltage of 1 Vpp (indicated by the colored regions) a transmission ranging from 43.33% to 56.66% can be modulated.
To quantify the signal quality of the system, we use the SINAD as a standard measure. The difference in signal quality of NRZ and RZ bit streams is shown in Fig. 4 (b). A random bit stream is sent through the system in both configurations. In NRZ mode, the signal could be transmitted with a SINAD of 16.66 dB, while the RZ mode brought an improvement to 26.90 dB. Therefore, all bit streams appearing in the following are transmitted in RZ mode. The random RZ bit stream represents a lower limit of the signal quality, as it contains an infinite number of frequencies, thus being the most challenging signal to transmit. A sinusoidal wave, as shown in Fig. 4 (c), on the other hand contains only one distinct frequency, hence being the upper limit for the system SINAD, calculated to be 37.87 dB. A snippet of a transmitted Zebra image is plotted in Fig. 4 (d).
3. Results and discussion
To assess the performance of the TFLN EOM-based electro-optical transceiver, we conducted a series of experiments based on image and video streaming. The selection of the image to be transmitted is inconsequential for our processor, hence in this particular investigation, a zebra image with a dimension of 960 × 640 px was employed. The oscilloscope measurement of the entire zebra image, which was transmitted through the system pixel by pixel, is illustrated in Fig. 5. The electrically encoded image sent from the DAC to the GSG Probe is represented by the blue line, while the green line represents the optical response signal of the PIC measured with the photoreceiver. The total time for the image, which consists of 614 400 px, was determined to be 246 ms, in accordance with the applied clock of 2.5 MHz. Extrapolating this to a Full HD image with a size of 1280 × 1080px, the transmission time through the processor is 829 ms corresponding to a Full HD image repetition rate of 1.2 Hz. The processor bandwidth is mainly restricted by the electrical bandwidth of the EOM, which has a 3 dB cut-off of 500 kHz. However, TFLN EOMs with bandwidths exceeding 100 GHz have been reported [10,17]. Due to the modularity of our setup, these can be plugged in to accelerate the full scheme, although they do not alter the principle of operation.
Fig. 4. Transceived bit strings. (a) 3 different varieties of sending the same bit string. Top: Data is encoded in analog bit values. Mid: To mitigate DC drifts that occur in case of a sequence of bits with the same polarity, every bit is sent twice, with positive and negative polarity (NRZ). Bottom: To further increase the modulator response, after every sent voltage pulse, the signal returns to 0 V (RZ). (b) Signal response on a random bitstring for NRZ and RZ voltage signal. For the NRZ case, the SINAD is calculated to be 16.66 dB, the RZ case shows significantly better performance having a SINAD of 26.90 dB. Due to the randomness of the signal, the maximum number of frequencies appears in the signal, giving a lower limit for the SINAD. (c) optical response of a sinusoidal voltage signal with RZ bit encoding. The sinusoidal equals a signal containing only one frequency, hence giving the upper limit for the bit transfer error of 37.87 dB. (d) Zoom-in of the optical response of a transmitted zebra image. The data is transferred using RZ bit encoding.
3.1. Image streaming
To demonstrate the resilience of our transceiver, we performed an image convolution in the CPU utilizing standard kernels, specifically the Identity, Prewitt operators, and a 5 × 5 Gaussian blur. Thereby, every image floating point operation of the applied Kernel with the zebra image is transmitted through the PIC. Figure 6 displays distinct convoluted images. While the identity delivers an indistinguishable image replica, Prewitt operators emphasize the horizontal and vertical edges of the images. Thereby, every image is sent through the transceiver according to the number of Kernel entries, which corresponds to 9 times for the 3 × 3 and 25 times for the Gaussian blur. Even though only a limited number of images is transmitted, this measurement demonstrates that our transceiver is capable of video streaming.
Fig. 5. Analog encoded zebra image. The output of the DAC is represented by the blue curve, whereas the response of the PIC is indicated by the green curve, which was measured using a fiber-optic photoreceiver.
Fig. 6. different convolutions of a zebra image. The original is shown atop, with the transceived identity. A Left and a right Prewitt kernel are applied for edge detection, with the combination shown in the green box. Finally, a Gaussian blur was performed on two images with different resolutions, as the blur is barely visible in the high-resolution image. Zebra image from public domain with CC0 license.
Fig. 7. Charge accumulation of star image. The original image is transmitted, while every pixel is summed with itself to recreate the image identity. The blurred image is obtained by adding each pixel with its subsequent. The difference between identity and blurred image is defined as the Prewitt operation.
3.2. Time integrating receiver
The NetCast architecture’s technological breakthrough lies in its principle of outsourcing linear algebra operations from cloud servers to “smart transceivers”, which results in reduced energy consumption and latency [1]. The transmitter periodically streams the weights of a CNN through amplitude-modulated encoding, while the accumulate operation is executed on the receiver side through charge accumulation [18]. To demonstrate our device’s capability of time integration, we encoded images optically by accumulating subsequent pixels, as shown in Fig. 7. We flattened the image and streamed its pixels successively through the transceiver. The detector readout was adjusted to achieve charge accumulation of two consecutive pixels. The identity of the image was transmitted by accumulating each pixel with itself, achieved by sending each pixel twice. The image was blurred by accumulating each pixel with its neighbour. Subtracting the blurred from the identity equals a Prewitt operation and reveals the left edges of the transmitted image. As anticipated, the “shoulder edges” are not visible since the left Prewitt kernel is not sensitive to such top-only edges. This measurement demonstrates the capability of our smart transceiver to perform accumulate operations utilizing charge accumulation, giving rise to delocalized computing architectures.
3.3. Transceiver energy consumption
The energy consumption of the transceiver is derived as a sum from the consumption of the transmitting EOM, which encodes electrical to optical data, and the energy needs of the photodiode receiver module. The power consumption of the laser is disregarded, as it can on the one hand serve as a source for multiple transceiver modules by splitting the light in different channels, on the other hand, due to its CW characteristics, the consumption is independent of the number of transmitted bits rather than being dependent on the operation time. Combined, splitting to 10 channels operating at 10 GHz would already decrease the energy needs per bit to a few fJ.
The determination of the energy consumed by the PIC during one video stream can be derived from the capacitance of the CPW, as well as the voltage changes that are applied to it. Consequently, the energy requirement is heavily influenced by the image function and the value of the consecutive pixels. However, to access the mean power consumption per transmitted sample, the energy dissipated per voltage pulse has to be approximated, which is derived by ${E_{pulse}} = \mathop \smallint \limits_{\min (V )}^{\max (V )} C \cdot {U^2} \cdot P(U )dU$, where P(U) is the probability distribution of each pulse height which is $\frac{1}{{1V}}$ in our case, and the integral boundaries being minimum and maximum of the voltage swing equaling –0.5 V and 0.5 V, respectively.
The CPW capacitance is simulated using Ansys HFSS, a finite element method (FEM) solver for high frequency electro-magnetic structures. For the utilized modulator, having a length of 1.7 mm, an average capacitance of 318 fF is simulated. This gives rise to an energy consumption of a mere ${E_{pulse}} = \mathop \smallint \limits_{ - 0.5V}^{0.5V} 318fF \cdot {U^2} \cdot \frac{1}{{1V}}dU = \frac{1}{{3V}} \cdot 318fF \cdot \frac{1}{4}{V^3} = 26.5fJ$ per voltage pulse. As previously mentioned, the transmitted sample consists of two pulses with opposite polarity, but same drive voltage. Therefore, the dissipated energy per sample is approximated to be 53fJ in average. Furthermore, as we used 8-bit digital to analog encoding, the energy consumption per bit concludes to be 55.4 fJ per sample (6.63 fJ/bit). Consequently, the total energy consumption for FullHD image streaming amounts to 109 nJ per FullHD image. The energy consumption of the DC bias follows ${E_{bias}} = CU_{bias}^2 = 318fF \cdot {({5.5V} )^2} = 9.6pJ$. Dividing the number of transmitted bits, which is heavily depended on the speed of the modulator and the transmitted image, this appears to be neglectable, as in our case of an image consisting of 614 400 px, the bias energy per sample calculates to 15.6 aJ.
The photodiode is a passive element, that has intrinsically no power consumption. However, a bias voltage of 9 V is applied, to increase the responsivity and gain of the InGaAs diode. The power consumption is calculated to be 24 µW. Hence, the energy per detection event depends on the number of detection events per second, reducing the consumption for high-speed operation at 10 GHz bandwidth to approx. 2.4 fJ.
Therefore, the overall transceiver energy consumption for 10 GHz operation can be approximated to be as small as 55.4 fJ per bit, outperforming the electronic energy limit per operation of 1 pJ [19].
4. Conclusion
The results of our experiments clearly showcase the feasibility and efficacy of utilizing TFLN EOMs as smart transceivers. The modulator’s impressive electro-optic properties enabled efficient and accurate signal processing, making it a promising candidate for various optical computing applications. The real-time processing capabilities, combined with its energy efficiency, suggest potential applications in image processing, communication systems, and neural networks. The proposed device acts as a blueprint variety of edge computing architectures, as its performance can be enhanced e.g., by wavelength-division multiplexing [1] and cross-bar-array arrangement [18].
Funding
Horizon 2020 Framework Programme (101017237, PHOENICS, 101046878, HYBRAIN Project); Deutsche Forschungsgemeinschaft (CRC 1459, EXC 2181/1 – 390900948, EXC-2082/1—390761711); Bundesministerium für Bildung und Forschung (Muniqc-Atoms, PhoQuant).
Acknowledgments
We thank Jochen Stuhrmann for assistance with the artwork in the figures.
Disclosures
The authors declare no conflicts of interest.
Data availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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