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Enhanced light extraction efficiency of a InGaN/GaN micro-square array light-emitting diode chip

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Abstract

A InGaN/GaN micro-square array light-emitting diode (LED) chip (micro-chip) has been successfully fabricated by the focused ion beam (FIB) etching technique, which can reduce ohmic contact degradation in the fabrication process of three-dimensional (3D) structure devices. Our results show that the micro-chip exhibits a similar current–voltage performance compared to the corresponding InGaN/GaN planar LED chip (planar-chip). At the driving current of 20 mA, the output power of the micro-chip is improved by 17.8% in comparison to that of the planar-chip. A relatively broad emission and enhanced emission intensity in the perpendicular direction are obtained in angular-resolved EL (AREL) measurements for the micro-chip. Three-dimensional finite difference time domain (FDTD) simulations have also proven enhanced emitted optical energy distribution. The enhancement mechanism is correlated to the increased light extraction efficiency (LEE) of the micro-chip, mainly owing to more photons from the exposed MQWs surfaces that can be efficiently extracted by the micro-square array.

© 2017 Optical Society of America

1. Introduction

GaN-based light emitting diodes (LEDs) have attracted much attention for potential applications in signaling, solid state lighting and large displays because of its lower energy consumption, longer lifetime and higher efficiency [1–3]. Recently, it has been proposed that three-dimensional (3D) GaN nanostructure LEDs (3D-LEDs) have excellent performance than conventional LEDs, owing to their fine crystallographic quality, high internal quantum efficiency (IQE) and light extraction efficiency (LEE) [4]. Both approaches of bottom-up and top-down have been reported to fabricate 3D-LEDs [5–9]. Due to the restricted growth conditions, it is difficult to control structural size/morphology naturally with sufficient precision and uniformity at the epitaxial interface for the former method. In contrast, the latter way as an etching technique is not just relatively simple and economic but easy to control the structural size and shape. Until now, a variety of top-down technologies have been reported for 3D-LEDs fabrication, for example, a self-organized nickel mask, nanoimprint lithography, laser holography, diblock copolymer lithography, and e-beam lithography etc [10–13]. However, an etch-back process is needed to achieve electrical injection for most 3D-LEDs device fabrications, which would cause the ohmic contact degradation owing to etch damage on 3D structures and thus affect the optical and electrical performances [14–16].

Focused ion beam (FIB) has been widely applied in milling semiconductor materials for transmission electron microscope (TEM) investigations and recently has been used for micro- and nanofabrication [17–20]. The major drawback of the FIB etching is its low throughput, making its unlikely application for mass production. However it is worth noting that single step fabrications approach as a unique advantage of FIB etching would significantly simplify 3D-LEDs chip fabrication process. In other word, FIB can etch device directly which does not require lithography, etch-back process, etc [21, 22]. Therefore planar LED chip can be etched directly to fabricate 3D LED chip by FIB, so as to reduce the ohmic contact degradation by avoiding the etch-back process. Consequently the effect of micro-square array on light emission can be investigated more precisely [23].

In our work, for a rapid fabrication approach we used the FIB etching as a 3D-LEDs chip fabrication method. Previous reports have demonstrated that microstructures have some analogous function as nanostructures to enhance LEE [24, 25]. In order to mitigate the factors of stress relief and improve fabrication efficiency, we fabricated InGaN/GaN micro-square array LED chip (micro-chip) on InGaN/GaN planar LED chip (planar-chip) by the FIB etching to study the effect of micro-square array on the optical and electrical properties of micro-chip.

2. Experimental details

Conventional GaN-based LEDs were prepared via the metal organic chemical vapor deposition (MOCVD) method. The schematic diagrams of layer structures for planar-chip and the fabrication process of micro-chip which begins with the aforementioned planar-chip are shown in Fig. 1. The operating wavelength of planar-chip is 450 nm. The planar-chip was put into a FIB-SEM (TASCAN, LYRA3) chamber for the direct writing. The chamber pressure was kept at about 10−7 mbar. The operated energy of gallium liquid metal ion for the FIB system was 30 kV. To exactly control FIB etching process, stream patterning project was used, which is created by importing FIB-etching parameters into the Draw-beam basic software such as beam current, etching shape, dwell time and beam overlap (space between filed square in the pattern) etc. Then the software created the project to specify a series of etching parameters. Consequently, the micro-chip was fabricated with the stream patterning project. In our design, an independent micro-chip (300 × 100 µm2) was completed by etching down to the substrate around the micro-square array on a whole chip, and a corresponding planer-chip with the same mesa size as the control device was fabricated using the same method. We fully utilized electrodes of the whole chip to act as electrodes for the two types of chips.

 figure: Fig. 1

Fig. 1 Schematic diagrams. (a) Layer structures of planar-chip. (b) Fabrication process of the micro-chip by FIB with stream patterning project. (c) The accomplished micro-chip. (d) Cross-sectional view of micro-square array. The etching depth of micro-square array exceeds the location of multiple quantum wells (MQWs), as shown in Fig. 1(d).

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However, although FIB is appropriate for the micro-chip fabrication, redeposition or implantation of residual ions may result in deterioration of the device performance with time [23]. To obtain an optimum device performance, the FIB beam current of 5 nA was used. Subsequently, wet etching method was used to remove FIB-induced damage [26, 27]. The micro-chip was dipped into 20% KOH aqueous solution at 60 °C for 2 minutes. The morphologies of micro-square array were carefully studied by scanning electron microscopy (SEM) at an acceleration voltage of 5 kV. The typical current–voltage (I–V) characteristics and light output power (LOP) performances were characterized by LED test system. The angular-resolved EL (AREL) measurement was performed to study the effect of micro-square array on light emission. The electromagnetic field distributions and the far-field radiation patterns were simulated using 3D-FDTD solution simulation software.

3. Results and discussion

A clear top view and a tilted view field SEM images of the fabricated micro-square array are shown in Fig. 2(a) and Fig. 2(b), respectively. The top layer material is indium tin oxides (ITO) with rough surface. The area of each micro-square is approximately 3 × 3 µm2 and the spacing between two micro-squares is about 4.3 μm. The micro-square array has high periodicity, comparatively smooth and faceted sidewalls, attributing to precise control and slight size effect of FIB etching. The micro-square array has been etched down to the n-GaN layer with an approximate depth of 1.5 µm, which exceeds the position of MOWs. The occupation ratio of micro-square array is about 9.4% in total area of the micro-chip.

 figure: Fig. 2

Fig. 2 The (a) top view and (b) tilted-view SEM images of micro-square array.

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Figure 3 displays typical current–voltage (I–V) characteristics between the two types of chips using a logarithmic current scale. It is known that ideality factor and series resistance of a Schottky diode can be calculated by applying the conventional drift-diffusion model [28, 29]:

I=IS[exp(qVD/nkT)1]
where I is the diode current at the applied voltage, Is is the diode reverse saturation current, q is the electronic charge, VD is the applied voltage, n is the diode ideality factor, k is the Boltzmann’s constant, and T is the absolute temperature. VD of the diode can be expressed in terms of the total voltage drop V across the series combination of the diode and the resistor.

 figure: Fig. 3

Fig. 3 The current–voltage curves of the micro-chip compared to the corresponding planar-chip plotting in semi-log scale.

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VD=VIRS

By plugging the Eq. (2) into the Eq. (1), the following equation can be obtained:

V=IRS+nkTqln(IIS+1)
As IIS, we can ignore the 1. So the electrical derivative function of the diode can show as following [28]:
E(I)=IdVdI=IRS+nkTq
According to the electrical derivative curve of Eq. (4), the slope and intercept are Rs.and nkt/q, respectively. Thus we can extract two parameters: ideal factor n and the series resistance Rs.

As demonstrated in Fig. 3, two current ranges can be distinguished for the two types of chips. In the current range of 10−6 A to 10−4 A, the forward voltages of both chips increase approximately from 2.3 V to 2.6 V. In the case, the 1og I-V curves of planar-chip and micro-chip have different slopes, represented by black and green dash lines, respectively. Through the Eq. (4), ideality factors are extracted to be nideal = 1.7 and nideal = 2.2 of the planar-chip and the micro-chip, respectively. Ideality factors between 1.0 and 2.0 are mainly dependent on the competition between the carrier drift-diffusion current (nideal = 1) and the generation-recombination current (nideal = 2) [30]. Ideality factors exceeding 2.0 are primarily attributed to the dominant mechanisms of trap-assisted tunnelling and carrier leakage for GaN-based LED devices. Therefore, the ideality factor of planar-chip (n = 1.7) signifies the dominance of diffusion-recombination current, reflecting the high quality of p–n junction of planar-chip. For micro-chip (n = 2.2), the tunneling current is mainly caused by etch damage from the energetic ion bombardment, including nitrogen vacancies, oxygen impurities and implanted etch ions, etc during the fabrication of micro-square array, which leads to lower forward voltage of the micro-chip than the planar-chip. The ideality factor of 2.2 nearly 2.0 for micro-chip indicates that few damage of the p–n junction in InGaN/GaN MQWs active region [31–33]. However, the damage is inevitable during etching process and it is difficult to be completely recovered by subsequent wet etching.

In the range of current exceeding 10−3 A, the series resistance Rs dominates, which depends on the additional contact resistance or the resistance of the material itself [29]. By using Eq. (4), the series resistances of planar-chip (Rsp) and micro-chip (Rsm) can be calculated to be approximately 17.1 Ω and 18.4 Ω, respectively. Comparing to the planar-chip, the slightly increased resistance value of 1.3 Ω demonstrates that the micro-chip obtains relatively stable series resistance and the increased value can be mainly attributed to the reduction of total active area [24]. Accordingly at the injection current of 20 mA, the forward voltages of micro-chip is 3.37 V which is higher than planar-chip with 3.31 V. Above discussions reveal that the I-V performance of micro-chip is similar to the planar-chip, so the FIB is a feasible and convenient etching technique to fabricate the micro-chip.

To further study the optical and electrical performance of micro-chip, the light output power (LOP) and the relative external quantum efficiency (EQE) performances of the two types of chips with injection current are measured at room temperature as shown in Fig. 4. At the driving current of 20 mA, the LOP of planar-chip and micro-chip are 108.0 and 127.2, respectively. Compared with the planar-chip, the LOP and the relative EQE of micro-chip are enhanced by 17.8% and 15.5%, respectively.

 figure: Fig. 4

Fig. 4 Light output power and the relative EQE as a function of current of the planar-chip and the micro-chip, respectively.

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For conventional LEDs, due to the lateral waveguide function and large difference in refractive index at the interface between GaN layer and air, most of the emission light from the MOWs would be reabsorbed internally. While for the micro-chip, the micro-square array can serve as clad for its surroundings to create a series of waveguides, so as to help channeling the light. More importantly, more exposed MQWs surfaces of the micro-square array can increase the escape opportunity of photons. Therefore, the LOP of micro-chip can be improved by fabricating the micro-square array. However the decline in the active area and increases the current at per unit area also affect the LOP of the micro-chip.

It is well known that EQE is expressed mainly by internal quantum efficiency (IQE) and LEE if the current injection efficiency is assumed to be 100%, and is given by [34]

ηe=ηint*ηext,
where ηint and ηext are IQE and LEE, respectively.

In our results, as the injection current increases, the blue-shift of electroluminescence (EL) emission peak for micro-chip is nearly same compared to the planar-chip. Therefore we believe the factor of stress relief would be less affected by the micro-square array fabrication. Consequently, the enhanced relative EQE indicates that the LEE of micro-chip can be enhanced by micro-square array fabrication.

To get better insight into the light extraction of micro-chip in the zenith direction, we completed AREL measurements under the injection current of 20 mA at room temperature. The measurement angle was in the range of 30° to 150° and angular resolution was 5° in the zenithal direction. Figure 5 shows the AREL intensity curves of the two types of chips plotted in a polar coordinate. For the micro-chip, the far-field pattern is broadened to 35° at the half maximum and displays a relatively broad emission, while it is about 40° for the planar one. It indicates that more photons from the exposed MQWs surfaces can be redirect by sidewalls to find their escape cones and extracted out into air. And the EL intensity of the micro-chip is increased of 17.1% than that of the planar-chip in the perpendicular direction. The enhancement is consistent with the results of LOP.

 figure: Fig. 5

Fig. 5 Angular distributions of EL intensities for the two chips plotting in the polar coordinate.

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In order to investigate the effect mechanisms of micro-square array on light extraction, 3D-FDTD simulations were performed to qualitatively simulate the electric field distributions and the far-field radiation patterns of the two chips. A single micro-square was taken into consideration. The absorbing boundary condition is perfect matched layer (PML). The far-field results were calculated from the near field results by the Fourier transform (FT). The simulation area of micro-square was 3 × 3 μm2. The height of the micro-square was set at 1.5 μm. A series of dipole sources (λ = 450 nm) were polarized around the micro-square in MQWs layer to simulate natural light. Meanwhile, an identical planar LED structure simulation model with same area, identical number and location of dipole sources was also applied in the same way to facilitate the light extraction performance comparison. Therefore the light extraction around the micro-square can be simulated.

Figure 6(a)-(b) show the calculated electric field distributions of the LEDs without and with the micro-square in the X–Z plane, respectively. As can be seen in the Fig. 6(a)-(b), more electromagnetic energy density concentrates in the micro-square LED in the vertical direction, compared to the planar LED, representing that the more photons can be efficiently extracted from the exposed MQWs surfaces and propagated to the farther region in the longitudinal direction. Top-view far-field radiation patterns for the micro-square LED and the planar LED are shown in Fig. 6(c)-(d). There is a very clear contrast between Fig. 6(c) and Fig. 6(d). For the planar LED structure, less optical energy per unit area can be obtained in the far-field region compared to the micro-square LED. The result of far-field radiation pattern for micro-square LED is an obvious evidence for enhanced recombination intensity, further implying that the light extraction can be increased by the sidewalls of micro-square array.

 figure: Fig. 6

Fig. 6 (a)-(b) 3D-FDTD simulations of the calculated electric field distributions of micro-chip and planar-chip at 450 nm, respectively. (c)-(d) Far-field radiation patterns at 450 nm for the micro-chip and the planar-chip, respectively.

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4. Conclusion

In conclusion, the micro-chip has been fabricated using the FIB etching technique. The technique can relieve the ohmic contact degradation in most 3D structure devices fabrication process, which is evidenced by nearly identical I-V performance between the two types of chips. For the micro-chip, the LOP is improved by 17.8% compared to that of planar-chip at the current of 20 mA and the emission intensity of APEL is increased of 17.1% in the perpendicular direction. Additionally, the FDTD simulations demonstrate that more photons from the exposed MQWs surfaces can be efficiently extracted and propagated to the farther region in the longitudinal direction. Consequently, FIB is a feasible and fast etching technique to fabricate the micro-chip and the LEE can be increased by micro-square array.

Funding

National Natural Science Foundation of China (21471111, 61475110, 61404089, 61504090, and 61604104); National Key R&D Program of China (2016YFB0401803); Basic Research Projects of Shanxi Province (2015021103, 201601D202029); Shanxi Provincial Key Innovative Research Team in Science and Technology (201605D131045-10).

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Figures (6)

Fig. 1
Fig. 1 Schematic diagrams. (a) Layer structures of planar-chip. (b) Fabrication process of the micro-chip by FIB with stream patterning project. (c) The accomplished micro-chip. (d) Cross-sectional view of micro-square array. The etching depth of micro-square array exceeds the location of multiple quantum wells (MQWs), as shown in Fig. 1(d).
Fig. 2
Fig. 2 The (a) top view and (b) tilted-view SEM images of micro-square array.
Fig. 3
Fig. 3 The current–voltage curves of the micro-chip compared to the corresponding planar-chip plotting in semi-log scale.
Fig. 4
Fig. 4 Light output power and the relative EQE as a function of current of the planar-chip and the micro-chip, respectively.
Fig. 5
Fig. 5 Angular distributions of EL intensities for the two chips plotting in the polar coordinate.
Fig. 6
Fig. 6 (a)-(b) 3D-FDTD simulations of the calculated electric field distributions of micro-chip and planar-chip at 450 nm, respectively. (c)-(d) Far-field radiation patterns at 450 nm for the micro-chip and the planar-chip, respectively.

Equations (5)

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I= I S [exp(q V D /nkT)1]
V D =VI R S
V=I R S + nkT q ln( I I S +1)
E(I)=I dV dI =IRS+ nkT q
η e = η int * η ext ,
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