1. Introduction

Dielectric or metallic photonic crystal (PhC) structures have been explored for a variety of applications with respect to frequency- or polarization-selective devices ranging from microwaves to optical operation frequencies [1]. One-dimensional (1D) periodic arrays of e.g. infinitely long parallel cylinders (or strips) embedded in a dielectric background material are typical building blocks for the setup of functional periodic devices. In terms of their proper analyses such spatial settings can be treated as two-dimensional (2D) according to their geometrical invariance in the direction of infinite extension (i.e. the $z$-direction in Fig. 1), to which the fields are also assumed to be invariant. Planar periodic structures with 2D lattice symmetries such as e.g. electromagnetic (EM) metamaterials, frequency selective surfaces (FSS) or photonic crystals (PhC) can be easily created from corresponding arrangements of 1D arrays [2–6]. Planar PhCs in particular have been exploited according to their specific light propagation characteristic showing distinct frequency ranges for allowed and forbidden wave propagation where the latter constitutes the so-called photonic bandgap (PBG). Waveguides can be obtained by symmetry breaking when removing e.g. one or a few rows from the PhC structures to achieve a low-loss propagation channel in the millimeter-wave and optical range [7–9] as well as highly directive radiation [10–13]. If two or three such photonic crystal waveguides (PCWs) are placed in close proximity, a corresponding set of coupled PCWs (C-PCWs) is formed where the optical power is efficiently transferred from one PCW to another [14]. PCWs guarantee good light confinement in the slow wave regime [15–17], which is a necessary condition for the enhancement of the nonlinear effects [18,19]. In nonlinear Kerr media, the induced refractive index change is proportional to the light intensity. Thus, with sufficient optical signal intensities, the Kerr effect can be used to influence another light signal which passes through the same medium forming the basis for all-optical signal processing [20,21].

 

Fig. 1. Schematic view of the three symmetric C-PCWs with guiding channels "$\mathit {a}$", "$\mathit {b}$" and "$\mathit {c}$" having the same width $w$ and separated by barrier layers of two PhCs each with number of layers $N_B$. The PhCs are composed of a hexagonal lattice of the circular air holes periodically distributed along the $x$-axis with a period $h$. The radius of the air holes is $r$, $\epsilon _s$ denotes the relative dielectric permittivity of the background medium and $w$ is the width of each PCW.

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All-optical logic gates, which are responsible for various logical operations in all-optical circuits, play a key role in ultrafast optical signal processing. Thus, it is of high relevance to realize fast, energy-efficient, and reliable all-optical logic gates. In this manuscript we demonstrate a complete working scheme for the realization of a true all-optical NOT logic gate, an AND logic gate and a NAND logic gate, which is a series connection of an AND and a NOT logic gate (Section 4.3). The latter is the most important, since any combinatorial logic function can be realized with enough NAND gates. For this purpose bandgap solitons in C-PCWs composed of an experimentally feasible planar air-hole type hexagonal PhC [22,23] with a nonlinear silicon background material are utilized. A characteristic of the working concept of the proposed all-optical logic gates is the virtually perfect digitalization of the involved time-domain signals inherent to the process of bandgap soliton transmission [24–31] in periodic nonlinear media [32,33]. The latter takes place when the operating frequency of the injected signal in the C-PCW is very close to the band edge of the underlying PBG thus enabling its nonlinear perturbation by other input signal(s). Note that an idea to realize all-optical logic gates using the bandgap transmission phenomenon was firstly proposed in our works [30,31]. However, the previously proposed formulation needed serious modifications because the authors could not successfully realize a cascaded topology. In this regard, the proposed manuscript represents a complete theoretical and numerical investigation of the topic.

All investigated gate topologies operate with temporal bandgap solitons having stable pulse envelopes during signal processing in the different C-PCWs, which is considered as one of the main advantages of the proposed working concept of the device. The resulting C-PCW-based building blocks can be cascaded using the output signal from one stage as a new input signal for the subsequent stage aiming at either different logic operators or multiple input logic gate architectures. It should be emphasized that due to the soliton nature of the signal pulses there is no need for intermediate signal amplification between different C-PCW stages or even different logic gates.

Since all logical operations can be performed using combinations of NAND gates, ultra-fast optical signal processing in future communication networks can be based on integrated all-optical logic gates with NAND functions [34]. In our studies we are considering a nonlinear PhC [35], since tight light guiding capabilities together with strong field localization is feasible enabling dense full-optical signal processing on the chip level. It should be noted that nonlinear PhC structures have already been introduced as a successful scheme to realize all-optical logic gates on the basis of e.g. multiple branch waveguide couplers [36,37], nonlinear ring resonators [38] and field localization in nonlinear slow-wave structures [39]. All-optical logic gates have been also constructed in the linear regime [40,41]. Our proposed topology has the advantage that it relies on the travelling-wave nature of the bandgap soliton transmission. Most of the PhC logic gates proposed so far are operated with continuous wave (CW) signals, whereas our approach supports realistic pulse operation in the true time domain where the latter nearly perfectly conforms to optical digital signal processing.

This paper is organized as follows. In Section II, our original self-contained, rigorous and numerically very fast formulation of the modal analysis for periodic structures [42–44] is briefly presented and applied to the modal analysis of three parallel C-PCWs as this structure will form the backbone of our functional all-optical logic gates. This full-wave method exploits the effectiveness of the transition matrix (T-matrix) approach, which characterizes the scattering nature of the unit cell. Lattice sums are then used to consider its periodic continuation whereas generalized reflection and transmission matrices are introduced in the case of layered arrangements of such periodic structures of finite extent. The exact calculation of the eigenmodes of the C-PCW system (i.e. the super-modes) is essential to the design of all-optical logic gates, since the operating frequencies should be properly chosen. The derivation of the bandgap soliton solution for nonlinear C-PCWs is presented in Section III. The analysis is based on the nonlinearSchrödinger equation using the slowly varying envelope approximation for the electric field together with the contribution of each counter-propagating space harmonic of the periodic structure to finally obtain a formal description of the temporal soliton’s formation. Hence, all features of nonlinear pulses and beam shaping can be qualitatively discussed in terms of the nonlinear Schrödinger equation. In Section IV the implementation of three ultra-compact functional all-optical logic gates in planar hexagonal air-hole type C-PCWs is discussed along with realistic full-wave time-domain simulations of the corresponding pulsed digital signal processing. First, the dispersion diagrams of the super-modes are analyzed using the method proposed in Section II to support a proper choice of the operation frequency. Next, a full-wave computational electromagnetics analysis that relies on the finite-difference time-domain (FDTD) method [45] is employed to demonstrate the successful operation of functional all-optical NOT, AND and NAND logic gates. Concluding remarks are given in Section V.

2. Modal analysis for coupled linear photonic crystal waveguides

In this section a self-consistent, rigorous and numerically very fast 2D formulation for the coupled 2D parallel PCWs is briefly discussed. The correct calculation of the modes in the C-PCWs is essential for the realization of functional all-optical logic gates, since it enables us to properly choose the operating frequency for bandgap soliton formation. A schematic view of the C-PCWs composed of three adjacent defect waveguides in a planar PhC made of circular air holes that are periodically distributed according to the hexagonal lattice symmetry with a common period $h$ is shown in Fig. 1. Without loss of generality we assume three symmetric C-PCWs, since a similar configuration will be used for the realization of fully optical logic gates in Section IV. However, it should be noted that the formulation is valid beyond just symmetric structures. It is very general, computationally fast and can be applied to any configuration of parallel C-PCWs. The guiding layers labeled $\mathit {(a)}$, $\mathit {(b)}$ and $\mathit {(c)}$ have the same width $\mathit {w}$ and are separated by two barrier layers made of two PhCs with a barrier thickness according to the number of layers $N_B$. The radius of the air-holes is $\mathit {r}$ and $\epsilon _s=\ n_s^2$ is the relative dielectric permittivity of the background medium. The number of layers $N$ of the upper and lower PhC slabs is chosen large enough, so that the attenuation constant related to the leakage of the power along the transverse direction ($y$ - axis) is negligibly small.

Let us assume that the guided electric field $E_x(x,y,t)$ in each region of the C-PCWs can be expressed as follows:

The linear system of Eqs. (2)–(6) can be re-written in the following compact form:

3. Soliton solution for coupled nonlinear photonic crystal waveguides

The periodically modulated $\mathit {x}$ - component of the electric field that propagates in the nonlinear C-PCWs can be written in the following form:

 

Fig. 2. Dispersion curves of the symmetric (blue curve and green curve) and the antisymmetric (red curve) super-modes for the $H$-polarized field in the three C-PCWs. The operating frequency for the realization of functional all-optical logic gates is $\frac {h\omega }{2\pi c}=0.232$, and it is marked by a red dot. The distributions of the magnetic field $H_z$ for the super-modes, as well as the geometry of the setup are shown in the corresponding insets.

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4. Realization of functional all-optical logic gates: numerical experiments and discussions

As already mentioned the planar PhC consists of a 2D hexagonal lattice of air holes that are introduced into a nonlinear dielectric background medium with a linear refractive index $n_s = 2.95$ in conjunction with a Kerr-type nonlinearity. The thickness of the PhC slabs corresponds to $N=5$ and the radius of the air-holes is $r = 0.32h$, where $h$ is the period of the PhC lattice. From a practical point of view, it is sufficient to have $N = 4$ layers along the $y$-axis to get a strong confinement of the modes in the guiding region while lowering the leakage along the transverse $\mathit {y}$ direction (in this case the propagation constant $k_{x0}$ is real [42]). Here we aim to use a typical semiconductor material with a relatively high refractive index, however, for practical application it is recommended to use materials with enhanced third-order nonlinearities such as e.g. hybrid organic- Si-on-insulator compounds [48]. The PhC barriers are composed of 1-layered structures (i.e. $N_B=1$), while the length of the PhC amounts to $30h$. This 2D model has already proved successful as a good approximation of the original planar 3D structure [22,23]. Under correspondingly adjusted parameters, the air hole-type PhC yields a PBG for the $H$-polarized field that extends over the frequency range of $0.230 < \frac {h\omega }{2\pi c} < 0.310$, where $c$ is the speed of light. The dispersion diagrams (Fig. 2) for the symmetric modes (blue and green lines) and antisymmetric mode (red line) of the three C-PCWs are calculated based on our original method described in Section II. The distributions of the magnetic field for the symmetric and antisymmetric modes, as well as the geometry of the C-PCW-based building blocks are presented within the corresponding insets. A comprehensive full-wave computational electromagnetics analysis is conducted based on the FDTD method together with uniaxial perfectly matched layer (PML) boundaries for truncating the simulation domain [45] at the operating normalized frequency $\frac {h\omega }{2\pi c} = 0.232$ indicated by the red dot in Fig. 2. The spatio-temporal discretization of the FDTD simulations corresponds to $\Delta x = \Delta y = 8.611 \cdot 10^{-8}$ [m] and $\Delta t = 1.9295 \cdot 10^{-16}$ [s], respectively. To speed-up the computation and to increase the numerical accuracy, we use dielectric averaging and 2x grid techniques.

Gaussian envelope pulses with carriers operating at the normalized frequency $\frac {h\omega }{2\pi c} = 0.232$ (indicated by the red dot in Fig. 2) are used as input signals. This operating frequency is properly chosen as it is located at the edge of the dispersion curve of the symmetric (super-) mode (blue line) where no other modes are excited in the linear regime. For the realization of functional true all-optical logic gates, we are thus only interested in this symmetric mode. Our numerical analysis has shown that the dispersion diagram represented by the blue line can be well approximated by a corresponding parabola, though taking only terms up to the square of the angular frequency into account. In our proposed scheme, the second derivative of the angular frequency with respect to the propagation constant (i.e. group velocity dispersion) has a positive value [51,53,54].

The all-optical logic gates proposed in the following sub-sections consist of three planar nonlinear C-PCWs as elementary building blocks. For the all-optical NOT logic gate we have one gate port (Port 1) and one output port (Port 2), whereas for the all-optical AND and NAND logic gates, two gate ports, namely Port 1 and Port 3, and one output port (Port 2) are required.

4.1 All-optical NOT logic gate

Figures 3 and 4 illustrate the realization of the proposed functional all-optical NOT logic gate. A continuous wave (CW) signal [cf. Fig. 3(b) and Fig. 4(b)], whose electric field is polarized parallel to the slab plane, with an amplitude of $A=0.956$ is launched into the C-PCWs through the middle Port 2. This port can be viewed as an "enable pin" of the NOT logic gate where the CW signal corresponds to the "enable signal" common in digital electronics. It drives the system towards the threshold. The injected peak power of the CW signal into Port 2 is chosen according to $\chi ^{(3)}E_0^2 = 0.1389$. This means that for silicon with a nonlinear refractive index $n_2={3}\cdot {10^{-18}}[\textrm {m}^2\cdot \textrm {W}^{-1}]$ [19,55], it follows that $E_0^2 = {2.2}\cdot {10^{18}} [\textrm {V}^2\cdot \textrm {m}^{-2}]$ (we excite the waves very close to the left edge inside the PhCs). A train of Gaussian pulses (in our analysis five Gaussian pulses) having an amplitude of $A = 0.812$ and the full duration at half maximum (FDHM) of $2.22$ ps are injected into Port 3 as illustrated in Fig. 3(c). The pulse repetition time is $15.43$ ps.

 

Fig. 3. Realization of a functional all-optical NOT logic gate: (a) no signal is injected into Port 1; (b) a CW signal with amplitude $A=0.956$ is injected into Port 2; (c) a train of five Gaussian pulses with amplitude $A =0.812$, FDHM of $2.22$ ps and a pulse repetition time of $15.43$ ps are launched into Port 3; (d) and (e) magnetic field distributions of the resulting signal pulses (i.e. the formed bandgap soliton pulse train) propagating in the C-PCWs; (f) magnetic field $H_z$ of the received signal at a distance $x=30h$ associated with Port 2; (g) the amplitude transfer curve, which represents the dependence of the maximum of the output pulse envelope versus the maximum of the input Gaussian pulse envelope. The peak level contrast between "1" and "0" amounts to 20 dB.

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Fig. 4. Realization of a functional all-optical NOT logic gate: (a) three Gaussian pulses with amplitude $A =0.52$, a FDHM of $2.22$ ps and a pulse repetition time of $(2\cdot 15.43)=30.86$ ps are launched into Port 1; (b) a CW signal with amplitude $A=0.956$ is injected in Port 2; (c) a train of five Gaussian pulses with amplitude $A =0.812$, FDHM of $2.22$ ps and a pulse repetition time of $15.43$ ps is launched into Port 3; (d) magnetic field distribution of the signal pulses propagating in the C-PCWs; (e) magnetic field $H_z$ of the received signal.

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Note that, at first, no signal pulse, i.e. $A =0$ (i.e. "0" of the NOT logic gate), is launched into Port 1 [Fig. 3(a)] and as the amplitude of the CW signal is also well below the threshold value $A =1.1$ no formation of the temporal solitons is possible. But if the amplitude of the CW signal exceeds the threshold value $A =1.1$, it could lead to the formation of the temporal solitons, which is not desired here. However, if a Gaussian pulse signal is injected into Port 3 the resulting increase in input power in the overall C-PCW leads to a shift of the dispersion curve (blue line in Fig. 2) towards lower frequencies, which is due to the Kerr effect. This shift continues until it eventually intersects with the dotted line in Fig. 2 that indicates the normalized operation frequency $\frac {h\omega }{2\pi c}=0.232$. This is the condition for the formation of a temporal bandgap soliton. Our theoretical studies have shown that the shift of the normalized angular frequency amounts to $\frac {h\Delta \omega }{2\pi c}=0.0016$ [53]. The carrier phases of the Gaussian pulses should be in line with the phase of the CW signal within a range of approximately $\pm 20 ^{\circ }$. Regarding the timing mismatch of the pulse envelopes, the proposed scheme is still functional when the time difference is as much as 0.5 ps. However it will effect the formation time of the temporal bandgap soliton, whereas this time constant is minimized when the carrier phases of the Gaussian pulses are in line with the phase of the CW signal (Fig. 3).

Figures 3(d) and 3(e) depict the magnetic field distributions of the temporal solitons propagating along the nonlinear C-PCWs. The output signal - a train of five temporal solitons - is registered at a distance $z = 30h$ (i.e. at the end of Port 2) and is shown in Fig. 3(f). Its amplitude is $A = 0.52$, the FDHM pulse width and pulse repetition time are equal to $2.22$ ps and $15.43$ ps, respectively. The registered signal characterizes "1" not only for the NOT gate, but also for all other logic gates studied in this work. Hence, this forms a stable system of all-optical logic gates that can perform a digital signal processing operations. This is possible only because of a unique feature of our proposed working concept, which we call perfect digitalization. This concept is demonstrated by the transfer curve for the NOT logic gate in Fig. 3(g). From the figure it follows that the maximum of the output envelope of pulses does not show any noticeable dependence on the maximum of the input Gaussian pulses. In other words, the input Gaussian pulses simply trigger the formation of stable temporal solitons with predefined amplitude and FDHM pulse width yielding a complete regeneration of the input signal during the optical digital signal processing.

Next, in order to vividly demonstrate the functionality of the all-optical NOT logic gate (i.e. output "0" at input "1"), we additionally inject three Gaussian pulses into Port 1 [Fig. 4(a)] with exactly the same characteristics as in the previous case. Namely, the amplitude is $A = 0.52$, the FDHM pulse width and pulse repetition time are equal to $2.22$ ps and $2\cdot 15.43=30.86$ ps, respectively. For this case the phase difference between the carriers of the Gaussian pulses through Port 1 and Port 3 should be around $180^{\circ }\pm 15^{\circ }$. From Fig. 4(e) it follows that only two temporal solitons are observed at the end of the C-PCWs and these solitons are formed by the Gaussian pulses through Port 3 indicated by the dashed red and green lines. The other three input Gaussian pulses are canceled out due to destructive interference and no solitons are formed. The characteristics of the output pulses in Fig. 4(e), namely their amplitude and width, are exactly the same as those in Fig. 3(f), which is an indication of the aforementioned digitalization phenomenon. We also note that the peak level contrast between the "1" and "0" output signal amounts to approximately 20 dB.

4.2 All-optical AND logic gate

The setup of a functional all-optical AND logic gate is illustrated in Figs. 5 and 6. As in the case of the all-optical NOT logic gate, a CW signal [as in Fig. 5(b) and Fig. 6(b)] is launched into the C-PCW-based building block through the middle Port 2 with the same amplitude $A = 0.956$. First, we show the operation of the all-optical AND gate given a "1" and "0" as input data while providing "0" at the output. For this purpose, a train of Gaussian pulses having an amplitude of $A = 0.52$ and a FDHM of $2.22$ ps are injected into Port 3 as illustrated in Fig. 5(c). The pulse repetition time is $15.43$ ps. The magnetic field distributions and the output signal at the end of Port 2 are depicted in Figs. 5(d), 5(e) and Fig. 5(f), respectively. No temporal solitons are formed and the output signal is virtually zero, as expected.

 

Fig. 5. Realization of a functional all-optical AND logic gate: (a) no signal is injected into Port 1; (b) a CW signal with amplitude $A=0.956$ is injected into Port 2; (c) a train of five Gaussian pulses with amplitude $A =0.52$, FDHM of $2.22$ ps and pulse repetition time of $15.43$ ps is launched into Port 3; (d) and (e) magnetic field distributions of the signal pulses (i.e. the bandgap solitons) propagating in the C-PCWs at different moments in time; (f) magnetic field $H_z$ of the received signal at a distance $x=30h$ associated with Port 2.

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Next, the performance of the all-optical AND gate is shown using a "1" and "1" as input data yielding the output "1". An additional pulse signal is injected into Port 1 with the same amplitude as in the case of Port 3 [cf. Fig. 6(a)], which leads to the formation of a temporal soliton inside the C-PCWs. Please note that the shape of the output signal is virtually the same as that of the input signal because of the perfect intrinsic digitalization of the working scheme [Fig. 3(g)]. The results are depicted in Figs. 6(d), 6(e) and 6(f), respectively. Note that the carriers of the input Gaussian pulses are in phase. However, as in the case of the all-optical NOT logic gate, the proposed scheme is still operational even for deviations of the carrier phases up to 20 degrees.

 

Fig. 6. Realization of a functional all-optical AND logic gate: (a) a train of five Gaussian pulses is launched into Port 3; (b) a CW signal with amplitude $A=0.956$ is injected into Port 2; (c) a train of five Gaussian pulses is launched into Port 3; (d) and (e) magnetic field distributions of the signal pulses; (f) magnetic field $H_z$ of the received signal. The peak level contrast between "1" and "0" amounts to 20 dB.

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4.3 All-optical NAND logic gate

The realization of a NAND gate is straightforward and can be achieved by using a series connection of an AND gate and a NOT gate. Figures 7 and 8 depict the corresponding realization of a functional all-optical NAND logic gate on a single (enlarged) PhC chip. Based on extensive computational electromagnetic analysis the output signals are retrieved [cf. Fig. 7(d) and Fig. 8(c)] demonstrating the operation of the proposed NAND all-optical gate. A necessary but challenging part for the realization of the all-optical NAND gate on a single chip concerns the "bridge" section. In order not to lose a portion of the temporal soliton power in Port 1 and Port 3, we removed a particular number of the air-holes in order to achieve a transition of the bandgap-soliton pulse from the AND logic gate into the NOT logic gate (the left side of the "bridge" section). The length of the "bridge" section should be chosen about six times larger than the period of the PhC. In order to avoid a substantial decrease in the amplitude of an output signal from Port 2 of the AND gate in the "bridge" section, a modification of the geometry is needed, namely, a decrease of the radii of the air-holes in the "bridge" section (marked by red in Figs. 7 and 8). Numerical experiments by using FDTD have shown that when the radii of the air-holes in the "bridge" section are taken as 0.18$\mathit {h}$, the NAND logic gate can be realized. This is because by decreasing of the radii of the air-holes, the dispersion diagram depicted in Fig. 2 is shifted towards the lower frequencies (the corresponding analysis has been conducted based on the formalism developed in [42]) and thus, the output pulse from Port 2, even after it loses a portion of its power due to back reflections, can pass the "bridge" - a single PhC waveguide - without a significant deformation of its form. Unfortunately, even after all these modifications, the amplitude from Port 2 of the AND logic gate has decreased due to a back-reflection (implicitly considered in the FDTD simulation of the overall NAND gate). However, due to the unique feature of our device - a perfect "digitalization" - the input parameters of the NOT logic gate can be adjusted to make the NAND logic gate operate properly. Another possibility to decrease back-reflection is the optimization of the "bridge" by properly adjusting the radii and position of the air-holes [56]. The further detailed optimization studies are crucially important for our device, since a substantial portion of the power due to the back reflection in the "bridge" region is a threat to the nonlinear operation of the AND logic gate. In particular, it could lead to the formation of unwanted temporal solitons in the AND gate. A possibility to further decrease the back-reflection in the "bridge" region is the introduction of a tilted PhC waveguide section as a "wave dump" that guides the reflected pulse from the NOT gate out of the structure into free space, where both the PhC waveguide bend [56] and the matching to free space may be subject to further refinements.

 

Fig. 7. (a) Realization of a functional all-optical NAND logic gate as a series connection of the AND logic gate and the NOT logic gate; (b) realization of the NAND logic gate on a single enlarged chip; (c) magnetic field distributions of the signal pulses in the NAND logic gate; (d) magnetic field $H_z$ of the received signal associated with Port 2.

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Fig. 8. Realization of a functional all-optical NAND logic gate: (a) Output signal from the AND logic gate is injected into Port 1 of the NOT logic gate; (b) magnetic field distribution of the signal pulses in the NAND logic gate; (c) magnetic field $H_z$ of the received signal.

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Finally, we also comment about the PhC propagation loss. In the numerical investigations we do not take into account the PhC propagation loss. However, based on experimental data found in [19], we can conclude that the propagation loss inside a single PCW is only about 8-9%.

5. Conclusion

We have proposed a functional scheme for a compact true all-optical NOT, AND, and NAND logic gate based on the phenomenon of bandgap soliton transmission using a realistic model of Kerr-type nonlinear C-PCWs. Key to the working concept behind the proposed all-optical logic gates is the observed perfect digitalization inherent to the associated processing of (stable) temporal solitons within the nonlinear C-PCW building blocks. Our studies were based on the weak-coupling approximation which allows for an analytical solution of the nonlinear Schrödinger equation for the time evolution of the slowly-varying envelope of the field, represented by the bandgap solitons. We believe that these studies provide a practical methodology for the design of ultra-compact nonlinear optical devices applicable, for example, to high-performance parity-bit checking [57].