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Large-scale integrated silicon photonic circuits suffer from two inevitable issues that boost the overall power consumption. First, fabrication imperfections even on sub-nm scale result in spectral device non-uniformity that require fine-tuning during device operation. Second, the photonic devices need to be actively corrected to compensate thermal drifts. As a result significant amount of power is wasted if no athermal and wavelength-trimmable solutions are utilized. Consequently, in order to minimize the total power requirement of photonic circuits in a passive way, trimming methods are required to correct the device inhomogeneities from manufacturing and athermal solutions are essential to oppose temperature fluctuations of the passive/active components during run-time. We present an approach to fabricate CMOS backend-compatible and athermal passive photonic filters that can be corrected for fabrication inhomogeneities by UV-trimming based on low-loss amorphous-SOI waveguides with TiO2 cladding. The trimming of highly confined 10 μm ring resonators is proven over a free spectral range retaining athermal operation. The athermal functionality of 2nd-order 5 μm add/drop microrings is demonstrated over 40°C covering a broad wavelength interval of 60 nm.
© 2015 Optical Society of America
1. Introduction
Athermal and wavelength-trimmable photonic systems are highly desirable for a multitude of applications in the broad field of integrated optics including telecommunication, nonlinear optics, microwave photonics, and optical sensing. In particular the optoelectronic integration of complementary metal-oxide semiconductor (CMOS) electronics with optical interconnects demands low power consumption satisfying the energy-bandwidth trade-off to tolerable levels [1–4]. Hence, power efficient devices are a basic requirement for a successful market launch of photonic-electronic integrated circuits (PEICs) in the emerging markets of data center- and telecommunications. Silicon photonics is envisioned to meet the demands of low-power on-chip optical interconnects, however, suffers from two inevitable issues which are the fabrication induced spectral device non-uniformity (NU) roughly specified in the order of 1 nm2/cm [5–8], and the temperature dependence of silicon photonic components around 0.1 nm/K [9–11]. The active compensation of these side effects increases the power consumption of very-large-scale integrated (VLSI) PEICs and the overall static and dynamic tuning can presently account for 20 – 30% of a photonic link, even with state-of-the-art manufacturing, latest microheater designs, and sophisticated mitigation concepts [12].
Commonly the manufacturing NU is counterbalanced by employing integrated microheaters, but as soon as the photonic components are fabricated in an athermal manner the strong thermo-optic coefficient (TOC) of silicon naturally loses its effect. Thus less efficient and tuning range limited (≤ 1 nm) solutions based on free-carrier dispersion (FCD) need to be applied to compensate NU for instance by DC-voltage biased pn junctions [13]. This solution requires each component to be doped and introduces additional losses due to free-carrier absorption and hence degrades the energy-efficiency for hundreds of photonic devices per wafer. Consequently, trimming methods are required to correct the device NU from manufacturing and athermal solutions are essential to oppose thermal drifts of the photonic components during run-time. Hence, a material platform that facilitates both athermal and efficient trimming strategies is advantageous in order to overcome these unavoidable detriments, preferentially carried out on wafer-scale and with a permanent step-and-repeat device trimming during wafer testing.
A mass fabrication compatible and cost-effective solution for the thermal compensation of VLSI photonic circuits are cladding materials with negative TOCs. Various materials like polymers [14–17], and more recently TiO2 which is CMOS-compatible and overcomes the polymer drawbacks of wetting, chemical instability, and heat degradation have been reported to effectively mitigate thermal drifts [18,19]. However, due to the relatively weak TOC of the employed materials the devices based on a strong de-confinement of the guided mode which implies higher propagation losses due to sidewall roughness, stronger leakage loss to the substrate, and higher bending losses that increase the device footprints of e.g. microring resonators (MRRs). Alternative passive compensation techniques include the confinement engineering of Mach-Zehnder-interferometers (MZIs) with asymmetric arm widths and lengths which is as well applicable for MRRs [20, 21], but MZIs occupy a relatively large device footprint.
On the other hand, due to the immanent need to eliminate fabrication imperfections of wafer-scale photonic systems different trimming techniques have been explored in the last few years. The methods are principally based on a permanent refractive index (RI) modification of either the waveguide core or the cladding material. Waveguide core trimming was realized by means of local oxidation e.g. using an electrically biased atomic force microscope tip [22], and local heating with high power lasers [23]. Further options include ion implantation inducing point defects [24], and surface modifications by amorphization and milling techniques using femtosecond laser pulses [25]. Recently, we published the UV-trimming of photonic components based on amorphous silicon-on-insulator (a-SOI) [26]. Cladding trimming methods were reported by straining the bottom oxide with an electron beam [27], and by using photo-sensitive materials like chalcogenides [28], or polymers that can be modified in RI by light or electron beam exposure [29,30]. Wafer-scale techniques that are capable to reduce photonic device NU were presented by atomic layer deposition techniques [31], and by deposition of silicon nitride overlays [32]. Furthermore, there is a trend towards mitigation strategies of spectral NU already on the device design level by adapting e.g. the evanescent couplers to fabrication tolerant dimensions or by using adiabatic taper sections in the vicinity of MRRs [33, 34]. All these methods alleviate the required tuning-power for NU compensation however do not solve the thermal drift issue.
Compared to the passive compensation techniques, recent works report alternative methods that rely on active strategies using feedback loops and inline stabilization of the devices via thermal heaters, pn junctions, or by poling electro-optic materials [35–38]. Although the active approaches add additional functionality to photonic circuits which make them favorable for certain types of applications, drawbacks are implicated by the additional power requirement of the feedback electronics and associated infrastructure and the more complex fabrication. Thus far, to the best of our knowledge, there is only one experimental work that realized both athermal and trimmable photonic devices for the less confined fundamental TM-mode by using a cladding combination of a photosensitive As2S3 chalcogenide glass and a negative TOC-polymer for the thermal drift compensation [39].
In this work, we present the first experimental proof of athermal and wavelength-trimmable photonic resonators for the fundamental TE-mode that are fabricated with highly confined 480 × 200 nm2 photonic wires based on a CMOS backend-compatible a-SOI photonic platform. The waveguides are top-cladded with a negative TOC TiO2-material to realize athermal functionality and are corrected for fabrication inhomogeneities by a spatially-selective and accurate UV-trimming method that can be carried out through cladding layers of SiO2 and TiO2 in step-and-repeat during device inspection on wafer-scale.
2. Athermal photonic devices
The design of the athermal MRRs was performed with finite-element-method (Comsol FEM) using the optical mode confinement model neglecting thermal expansion and without considering stress-induced effects in the waveguide cross section simulations. Due to the negligible contribution the waveguide curvature is disregarded. The cladding shape is adapted from a line-of-sight deposition model [40]. The athermal condition is satisfied when the guided mode index is stable over temperature . In case of our three material system the governing equation is given by
with ni and Γi as the RIs and confinement factors of the bottom oxide (Box), a-Si:H core, and TiO2 cladding materials. Further the temperature dependent resonance wavelength shift (TDWS) is determined from Eq. (2) with ngr as group index and αSi = 2.6 · 10−6K−1 as the dominant thermal expansion of the silicon substrate [41].We developed a relatively low nTiO2 = 2.02 amorphous TiO2-material by DC-sputtering that retains a strong mode confinement and in addition exhibits a high negative TOC of . Optical simulations for the fundamental TE-mode that match the athermal condition at 1550 nm wavelength for different cladding layer thicknesses are shown in Fig. 1(a). The optimal TiO2 cladding thickness was determined to be tTiO2 ≈ 450 nm in order to realize athermal photonic devices at T = 30°C based on our standard 480 × 200 nm2 photonic wire waveguides. Slight notching that may occur during the sputtering process due to the waveguide shadow-effect was neglected. The material RIs and TOCs that were implemented in the optical simulations are summarized in Table 1 including the confinement factors of athermal waveguides with TiO2 top cladding in comparison with SiO2-cladded photonic wires. The TDWS for both cladding materials that were calculated according to Eq. (2) are presented in Fig. 1(b).
Fig. 1 Optical simulations of the athermal photonic wires: (a) Guided mode index and temperature sensitivity. (b) Resonance wavelength shift of conventional SiO2- and athermal TiO2-cladded resonators over temperature with a mode simulation inset.
Table 1. Refractive indices, thermo-optic coefficients, and simulated confinement factors of 480 × 200 nm2 a-SOI photonic wires with 400 nm TiO2 and SiO2 () top cladding. References that support these data are provided.
The high waveguide core RI accompanied with the low RI and high negative TOC cladding implicates several beneficial properties compared to weakly confined athermal waveguides. Due to the relatively low TiO2 cladding index the guided mode core confinement is conserved with Γc = 0.67 compared to Γc = 0.74 for a SiO2 cladding which favors low bending losses and hence compact device footprints. An important consequence is that wide free spectral range (FSR) MRRs are realizable which support a large number of parallel data channels guided within one bus waveguide relevant for dense wavelength-division multiplexing (DWDM), e.g. Nch ≥ 16 for R = 5μm radius MRRs, even further scalable to R ≈ 2μm resulting in Nch ≥ 32 channels on a 100 GHz-grid [44]. In addition, the strong confinement avoids excessive substrate/interlayer leakage and absorption loss to closely separated metal layers, which minimizes the need for thick optical isolation interlayers that are required in case of low-confined waveguides that need to expand the mode field in the weak negative TOC cladding. Alternative methods that use Box under-etching fulfill the same purpose and moreover decrease the power consumption required for the active tuning by heaters [9, 45–47], however, are not necessarily multilayer compatible which due to our belief indeed will gain importance in future PEICs. Furthermore, wider waveguides suffer less from detrimental sidewall roughness [48], and the impact of fabrication imperfections due to small variations in the waveguide width and height result in considerably larger spectral NU in case of narrower waveguides [49, 50].
3. Athermal device characterization and trimming results
Optical add/drop MRRs were fabricated with hydrogenated amorphous silicon (a-Si:H) material deposited on thermal oxidized Si-wafer substrates [51]. Grating couplers were used to launch the NIR light into 480 × 200 nm2 photonic wires which exhibit linear propagation losses of 3.25 dB/cm at 1550 nm and about 2 dB/cm at 1620 nm for the TE-mode as determined by virtual cut-back measurement for a simple I-line polymer resist cladding. As reported in [52], deposited SiO2 can substantially reduce the losses compared to an I-line polymer, so that propagation losses of 1 dB/cm are realizable with a-Si:H photonic wires as recently reported [53]. The main loss contribution of our waveguides originates from sidewall roughness. With μm-dimensioned waveguides we measured ≤ 0.5 dB/cm and from photonic wire coupled high Q ≈ 106 microdisks we derived losses of about 0.65 dB/cm [54, 55].
The TiO2 top cladding was DC-sputtered from a titanium target at a power of P = 450 W and with O2/(O2+Ar) (1/5) dilution. The surface roughness of the thin films were measured with atomic force microscopy and resulted in σrms = 0.25 nm, σrms = 1 nm, and σrms = 2.5 nm for the SiO2, a-Si:H, and TiO2 optical layers, respectively. The TiO2 absorption was not determined, however, DC-sputtered TiO2 waveguides were recently reported with about 1.2 dB/cm at 1550 nm [56]. Instead we provide a comparison measurement of MRRs in notch and add/drop configuration with TiO2 and SiO2 top cladding as presented in Fig. 2. The relevant data were extracted by using a Lorentz fitting and the summarized key metrics are provided in Table 2. The MRRs have similar quality and exhibit comparable values as typical SOI MRRs with same size and coupling gap dimensions [10]. Thus far the whole photonic chip was covered with TiO2, alternatively a local deposition or structuring only on top of the athermal devices is possible. The more important property of sufficient UV-transparency for the photonic device trimming was directly confirmed by the experiments. The 1st-order 10 μm radius MRRs were realized with a 150 nm gap, whereas the 2nd-order 5 μm radius add/drop dual-microrings (DRRs) were designed with a 140 nm gap for the bus-to-ring and a 485 nm ring-to-ring coupling gap. The 3 dB-bandwidth of the devices were determined to be Δλ3dB = 150 pm and Δλ3dB = 1.2 nm at λ = 1.55 μm, respectively.
Fig. 2 Comparison of TiO2- and SiO2-cladded microring resonators: (a) TiO2- and (b) SiO2-cladded notch filters with Lorentz fits inset. (c) TiO2-cladded and (d) SiO2-cladded add/drop resonators.
Table 2. Measured microring resonator key metrics for a-SOI photonic wires with a 400 nm TiO2 and a 1μm SiO2 top cladding.
The athermal resonators were characterized with spectral transmission measurements and in temperature drift experiments. The optical characterization and inline UV-trimming setup and micrographs of the athermal photonic devices are presented in Fig. 3. The temperatures were adjusted by a thermo-electric-controlled (TEC) chip mount. The trimming experiments were carried out with a continuous wave UV-laser at λ = 405 nm wavelength (Eλ ≈ 3.01 eV). The trim-light was fiber-collimated into a single-mode UV-fiber and the cleaved facet (MFD=2.59 μm) was positioned on top of the photonic devices. The signal from the tunable laser source (TLS) was guided through an erbium-doped fiber-amplifier (EDFA), followed by a polarization controller which maximized the fiber-chip-coupling of the TE-polarization. At the chip output the signal was 3 dB-split in order to inline monitor the MRR spectra during trimming with a spectrum analyzer (OSA) and to facilitate a high resolution measurement with a photo-detector (PD). More details about the time dependence of the trimming with different power levels, the trimming range and velocity, and the tuning accuracy have been reported for uncladded a-SOI photonic wires [26]. The UV-exposure results in a permanent and slight decrease in the a-Si:H RI and hence allows modifying the guided mode properties and adjusting the spectral characteristics of photonic components.
Fig. 3 (a) UV-trimming and optical measurement setup. Athermal photonic devices: (b) 10 μm radius add/drop MRR. (c) Add/drop dual-ring resonator with 5 μm radius.
3.1. Optical characterization of the athermal resonators
First the temperature dependencies of the single MRRs were characterized by tuning the temperature of the chip mount and the athermal devices were compared with same sized R = 10μm MRRs with SiO2 cladding. The measurements are presented in Fig. 4. The experimental results are in good agreement with the optical simulations of Fig. 1 that targeted a compensation close to T = 30°C. We attribute the difference between the simulated data and the experimental results to small variations in the measured TOCs, thermal expansion and strain of the material stack, and to slight deviations of the waveguide dimensions and the top cladding thickness. In the athermal region between T = 30 – 40°C the devices exhibit an average TDWS of 6 pm/°C as presented by the resonances in Fig. 4 (a). The MRR is slightly overcompensated at T = 30°C and blue-shifts up to the athermal point at T ≈ 35°C after which the TDWS changes direction and moves back to longer wavelength. As expected the effect due to the confinement ratio variations over temperature is distinctly evident what actually is a drawback of using materials with high TOC-difference and remains a trade-off between strong mode confinement and inherent advantages vs. athermal range. Nevertheless, the TDWS is significantly reduced compared to Δλres ≈ 90 pm/°C which was determined for same dimensioned MRRs with SiO2 cladding as shown by the measurement in Fig. 4 (b). A direct comparison in the temperature range of T = 25 – 50°C is presented in Fig. 4 (c).
Fig. 4 (a) MRR drop port spectra of an add/drop filter with TiO2 cladding over a 10°C temperature range. (b) MRR through port spectra over ΔT = 10°C with SiO2 cladding. (c) TDWS comparison of SiO2- and TiO2-cladded waveguides.
An effective TDWS mitigation strategy to virtually minimize thermal drifting is the usage of box-like filters with flat-top spectra which can be realized by 2nd-order filters. Although the resonances still suffer from a similar TDWS the absolute power at the filter output remains constant over a broader temperature range. This is experimentally demonstrated with compact DRRs having a wide FSR ≥ 18 nm. The devices are as fabricated and were not actively-tuned or wavelength shifted by UV-trimming. The measured spectra for different temperatures are presented in Fig. 5 in which the athermal operation is expanded to ΔT ≥ 30°C without a drop in output power. It should be noted that 70°C is the maximum set temperature of the TEC and the TDWS is just at the parabolic turning point from which it is estimated that highly confined athermal DRRs of these dimensions can be realized over ΔT ≥ 50°C if a 2 dB power drop is acceptable. The athermal functionality remains constant over a broad wavelength interval of Δλ ≥ 60 nm and beyond.
Fig. 5 Close-up view of the dual-microring spectra showing athermal functionality over a temperature range of ΔT = 40°C and Δλ ≥ 60 nm wavelength interval. The spectra belong to the same device and are spaced by the FSR for a better visibility.
3.2. UV-trimming of athermal resonators
As already discussed athermal VLSI photonic systems will not unveil their true potential before the single devices can be adjusted in their spectral properties to counterbalance fabrication NU. We use a UV-trimming through the TiO2 top cladding to demonstrate the capability to correct athermal photonic circuit components. The trimming experiments were exercised as follows. The fiber was positioned on top of the photonic devices using alignment cameras and the MRR spectra were stepwise blue-shifted to shorter wavelength by irradiating the photonic wire at different locations. Because the trimming is spatially selective the fiber with a power of P = 5 mW at the output facet was moved along the MRR surface area and the TDWSs were determined intermediate the UV-exposures. The temperature dependence of the R = 10μm MRR that was trimmed in four successive Δf ≈ 100 GHz steps is presented in Fig. 6 (a) with the measured data points linked to guide the eye. The graph shows that the device keeps its athermal functionality while the resonance is shifted to shorter wavelength.
Fig. 6 (a) Athermal operation of an add/drop resonator after UV-trimming the device spectra by ≈ 100 GHz steps at T = 30°C. (b) Measured resonance peak positions (markers) that shift to shorter wavelength due to the trimming procedure. (c) A close-up view of a resonance peak blue-shifted over one FSR.
Furthermore, the trimming range was evaluated by blue-shifting the spectra over an entire FSR of Δλres ≈ 9.5 nm. Fig. 6 (b) summarizes the shift of the resonance peak positions (markers) within the measured wavelength range plotted as a function of the UV-irradiation steps that were carried out at different MRR locations. The microring spectra are evenly shifted to lower wavelength as can be observed from the equidistant lines. The MRR quality does not substantially vary due to the UV-light exposure which was evidenced from the drop port Q-factors. The average values in the 1530 – 1580 nm wavelength interval were determined to range between Q = 7700 – 9100. A close-up view of one separate resonance peak that is successively trimmed over one FSR is shown in Fig. 6 (c).
4. Discussions
4.1. Experimental result and application area discussion
Athermal and wavelength-trimmable MRRs that are based on TiO2-cladded a-SOI photonic wires are presented. The proposed material platform allows realizing power-efficient VLSI photonic circuits because the components will maintain their functionality even under detrimental and unavoidable temperature fluctuations. The athermal devices were designed for the highly confined TE-mode using 480 × 200 nm2 photonic wires. In comparison to low-confined waveguides this approach yields advantages in terms of compact device footprints, low photonic wire propagation and absorption losses in the vicinity of metals, reduced substrate and interlayer leakage, and tolerable radiation loss in tight bends. Apart from the high integration density, the photonic components exhibit additional functional merits for instance wide FSRs that facilitate a large number of parallel DWDM channels including the advantages of high data rate capability due to the fast cavity built up times of short circumference MRRs.
While conventional photonic wire based MRRs with SiO2 cladding and quality factors of Q ≈ 104 already fail to keep the 3 dB power level at the target wavelength for ΔT ≤ ±1°C, athermal devices can extend this range to tolerable levels. From the simulations and the experimental results we determined that for instance a 2nd-order filter that is designed with Δλ3dB = 0.6 nm can be stabilized over ΔT = 40°C and up to Δλ = 100 nm covering the whole C/L-telecommunication wavelength bands without any significant performance drawback due to thermal drifts. Such specifications are assumed to be sufficient to mitigate or completely avoid side effects due to local temperature fluctuations that are introduced by spatially close active-tunable photonic devices or thermal hotspots originating from CMOS-electronics due to varying work loads during operation that are reported to range between ΔT ≈ 20 – 40°C [11,58]. Self-evidently the method is not limited to MRRs but is applicable for all kinds of integrated waveguide based devices like Mach-Zehnder-interferometers, arrayed waveguide gratings, power-splitters, and other important building blocks.
The fundamental drawback of commonly reported athermal devices that lack a possibility to counterbalance the inevitable fabrication imperfections in a passive way without additional power consumption is opposed by a UV-trimming method that facilitates correcting a-SOI photonic devices over a broad spectral range and with high spectral accuracy [26]. Also, different waveguide types like horizontal slot and rib-loaded waveguides will be trimmable to some extent, dependent on the confinement ratios. It is likely that not only passively stabilized photonic components are required for complex PEICs. Hence, the UV-trimming can be employed to adjust the spectral disorder of single components e.g. in filter banks relative to each other and to reduce the static power consumption and to use the strong a-Si:H TOC with a TDWS of Δλres ≈ 90 pm/°C for the active tuning and filter reconfiguration. Furthermore, it is worth noting that high TOC TiO2-cladded waveguides can exhibit 2–3 times higher heater efficiency e.g. used for phase shifters if the mode is widely de-confined into the cladding or directly mode-converted to TiO2 waveguides that can be structured in a second lithography step.
Presently, technological implications were determined in the stability of the TiO2 material properties over a time-scale of about three weeks after deposition. Both trimmed and untrimmed TiO2-cladded devices suffered a quantitatively comparable red-shift of the device spectra. Since the TiO2 was not topcladded against the ambient environment the effect is most-likely attributed to strain relaxation of the a-SOI/TiO2 material stack that results from a compressive stress release and/or a slight decrease of the TiO2 RI which needs to be further investigated. Similar phenomena were recently reported for electron-beam evaporated TiO2 material where a slight hysteresis curve was measured in the TDWS experiments [43]. Furthermore in [57], TiO2 waveguides were investigated with different cladding shapes thereby identifying that stress can influence the TDWS to a similar extent as the intrinsic material TOC. We agree to the conclusions of both surveys that further research studies are required to better understand the origin of the TOC-variations including the correlations with the material density and the contribution of the thermal expansion coefficient.
However, the observation does not violate the overall principle to fabricate athermal and UV-trimmable a-SOI devices because this is no inherent TiO2 material property and numerous reports do not encounter this phenomena. Furthermore, we think that slight adjustments in the deposition process, a low temperature post-fabrication annealing step at T ≈ 200°C, and/or an additional cladding layer deposition on top can solve this issue. The influence of the a-Si:H material was excluded with reference measurements from SiO2-cladded MRRs that were UV-trimmed and remained stable in the spectral characteristics over the same time period.
In addition to the employment of the material platform for selective filtering and multiplexing, a-SOI is in particular promising for nonlinear photonics and optical sensing. Since a-Si:H can be deposited on a variety of substrate materials, including different glasses and flexible substrates like e.g. plastics, it is well suited for the detection of physical quantities and for the label-free sensing of biochemical substances relevant in point-of-care-diagnostics and optofluidic lab-on-chip biosensors [59, 60], in which temperature often plays the most deteriorating role. Dependent on the deposition conditions, a-Si:H possesses a high nonlinear figure of merit which is advantageous for numerous all-optical and ultra-fast signal processing applications [61–67]. These applications may benefit from a wavelength stable athermal solution that avoids the thermal device dynamics of free carrier recombination [67], and the temperature induced optical bistability already occurring at relatively low powers [68].
4.2. Considerations on CMOS-backend and heterogeneous material integration
The a-Si:H and TiO2 deposition processes are carried out at low temperatures of T ≤ 300°C and hence the proposed material platform is not restricted to a single optical layer, but can be extended to multi-stack photonic circuits, and allows the integration with CMOS-electronics at the backend and the inclusion of heterogeneous fabrication processes as will be briefly discussed in the following. The technological integration of PEICs can be at first instance categorized into two major approaches: The front-end-of-line (FEOL) integration targets to develop the photonic circuits within the first layers directly at the transistor level, whereas the back-end-of-line (BEOL) integration aims to fabricate the photonic layers on top of the metal interconnects using low-temperature processes [69]. Although impressive progress has been reported for monolithic-FEOL PEICs, the integration of photonic circuits with the existing microelectronic process chain still is an issue, in particular for future VLSI PEICs.
Low-loss silicon based photonic materials like SOI and silicon nitrides (SiN) are widely anticipated for FEOL and BEOL integration, respectively, because the materials are already used in microelectronics industry and rely on existing and mature infrastructure. In addition, low-loss a-SOI/TiO2 is a viable material platform for the photonic backplane because the materials can be deposited on top of the readily fabricated microchips at the BEOL-stage with minimal interventions into the electronic fabrication chain. A-Si:H exhibits a high and trimmable RI of n ≈ 3.5 relevant for highly integrated photonic circuits and a low absorption in the near-infrared [70–73], down to 0.04 dB/cm at 1550 nm [74]. The material can be deposited with high uniformity and reproducibility in multiple layers and supports vertical stacking as already common practice with electronic interconnects [75,76]. The photonic layers can be then linked by optical vias based on inverse tapered directional couplers, gratings, or MRRs which have been already demonstrated on a-Si:H material platform [77–81].
Thus, a-SOI/TiO2 provides a basis for athermal and trimmable PEICs in form of the much anticipated 3D-integration of photonic layers on top of electronics [3], which minimizes the distances of electronic and photonic building blocks, simplifies the complexity of routing, and avoids excessive latencies. A vertical integration relaxes the footprint discrepancy, the isolation layer thickness at the FEOL, and the difference in critical dimensions of the electronic and photonic nodes, e.g. 22 nm vs. 500 nm. Furthermore, a 3D-integration facilitates the opportunity to distribute optical signals on different layers that can be separated either by their functionality or their diverse fabrication demands and hence favors the usage of heterogeneous fabrication processes and materials which can be included outside the relatively rigid CMOS-process line [82]. Although the manufacturing processes need to comply with the a-Si:H dehydrogenation temperature (T ≥ 350 – 400°C), this is no major obstacle for most applications if the process sequences are arranged accordingly.
For the modulator integration various promising approaches that rely on deposited silicon have been reported by doping the a-Si:H material and/or by transforming a-Si to poly-silicon using excimer-laser annealing so that BEOL electro-optical modulators become realizable [83–85]. Although the modulators will probably not reach the speed of state-of-the-art silicon based devices with 40 Gb/s and beyond, less fast but more parallel channels with e.g. 10 Gb/s are considerable solutions in terms of energy/bit [86]. Alternative heterogeneous methods of concern are novel plasmonic modulators [87], for instance based on organic hybrids [88], and low temperature deposited or bonded electro-optic materials like e.g. BaTiO3 or LiNbO3 [89, 90]. Also, ultra-fast all-optical modulation schemes based on a-Si:H can be envisioned, in particular, if solutions for optical memories and buffers become realizable.
5. Conclusions
We experimentally demonstrate a novel and viable method to fabricate athermal and wavelength-trimmable photonic devices based on backend-compatible a-SOI/TiO2 material platform. The approach counteracts two immanent challenges in reducing the power-consumption of VLSI photonic circuits because it avoids the active-correction of fabrication inhomogeneities and counterbalances thermal fluctuations. Hence, the passive athermal devices can operate energy-efficient over a broad temperature range and wavelength interval. The low-cost UV-trimming allows to permanently fine-trim athermal photonic devices with high accuracy and to correct unavoidable fabrication imperfections in a step-and-repeat process through SiO2 and TiO2 cladding layers during device inspection. This work provides a potential solution to realize power-efficient photonic filters that can be fabricated in form of a 3D-optical backplane on top of CMOS-electronics relevant for optical interconnects. Furthermore, we think the method can be utilized for integrated-optic devices in the areas of telecommunication, optical sensing, nonlinear optics, and RF-photonics. Nevertheless, more research studies are required to better understand the fundamental physics of the UV-trimming and the refractive index/thermo-optic coefficient correlation of TiO2 and to confirm this proof-of-principle work under the constraints of e.g. guiding high-power laser light or long-term temperature stability relevant for some applications.
Funding Information
The authors like to thank DFG grant FOR-653 for partial funding of the fabrication expenses. Further this publication was supported by the German Research Foundation (DFG) and the Hamburg University of Technology (TUHH) in the funding programme “Open Access Publishing”.
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