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An optical interconnect transmitter based on guided-wave silicon optical bench is demonstrated. The guided-wave silicon optical bench (GW-SiOB) is developed on a silicon-on-insulator (SOI) substrate. The three-dimensional guided-wave optical paths on the silicon optical bench are realized using trapezoidal waveguides monolithically integrated with 45° micro-reflectors. Such three-dimensional guided-w ave optical paths of SiOB would simplify and shrink the intra-chip optical interconnects located on a SOI substrate. The clearly open eye patterns operated at a data rate of 5 Gbps verifies the proposed GW-SiOB is suitable for intra-chip optical interconnects.
©2012 Optical Society of America
1. Introduction
The growing demand for a wide variety of datacom and telecom services requires a dramatic increase in the throughput of routers, switches, and WDM terminals. However the attenuation, leaks, and EMI problems are critical for high-speed signals in the electrical interconnects of rack-to-rack, board-to-board, chip-to-chip, and even intra-chip applications. Such problems become a bottleneck in improving system performances. Therefore, optical interconnects have been increasingly sued to replace electrical interconnects such as parallel multiwavelength optical subassembly (PMOSA) [1], small form-factor pluggable (SFP) modules [2] and quad small form-factor pluggable (QSFP) modules [3] for rack-to-rack [2, 3] and board-to-board [1, 4, 5] interconnects, optical printed circuited boards [6–14] and surface plasmon polariton waveguides [15] for chip-to-chip interconnects [6–8, 14, 15], and SOI-based guided-wave paths [16–21] for intra-chip interconnects
Optical interconnects support higher data-rate, increased bandwidth density, and more compact connections. The increasing employ of optical interconnects has been a direct result of cost down, decreasing power, and increasing density. In addition, the bandwidth increment of computer systems rises the requirement of optical interconnect to (or in) the processor at inter-chip or intra-chip scales. Such inter-chip or intra-chip connections always accompany with active components and optical-waveguide structures for improving data-rate, power-efficiency, and density of optical interconnect modules. As considering the intra-chip optical interconnects, most of demonstrations are realized using silicon waveguides based on the silicon-on-insulator (SOI) substrate [16–21], including photodetector-to-waveguide interconnect [16, 17], photodetector-to-modulator interconnect [18], and laser-to-waveguide interconnect [19–21]. The improvement of optical coupling efficiency between active devices and waveguides is the key issue for intra-chip interconnects, especially for laser-to-waveguide interconnects. Three approaches, including evanescent wave coupling [19, 21], surface plasmon coupling [20], and grating coupler [22] are adopted for the laser-to-waveguide coupling. Using the evanescent wave coupling, the threshold current for laser-to-waveguide interconnects is 50 mA [21] and the threshold optical pumping power for laser-to-waveguide interconnects is 50 mW [19]. Using the surface plasmon coupling, the threshold current for laser-to-waveguide interconnects is as high as 500 mA [20]. However, such power consumptions for both coupling schemes are not available for real optical-interconnect applications. Grating couplers with high coupling efficiencies of 69.5% have been demonstrated on the SOI substrate by introducing a reflector under the gratings [22]. The specific incident angles for grating couplers are inevitable under the phase matching condition. It means that laser devices are difficult to be integrated into the on-chip optical interconnect module with grating couplers under a unique tilted angle. Therefore, an efficient approach to improve the optical coupling is important for intra-chip interconnects.
For on-chip optical interconnects, the polymer waveguide with 45° slants has been developed [23]. However, the 45° slants are formed using tilted photolithography. Without bordering with silicon-based 45° reflector, the polymer waveguide is difficult to be integrated with the active devices such as VCSELs and PDs. However, as the polymer waveguide being fabricated in a 45° trench developed on a silicon substrate, it would facilitate the integration of VCSELs and PDs with the polymer waveguide. For such polymer-type coplanar light paths, the active devices should be assembled on the same facet of silicon substrate. If some functional ICs would be fabricated on the same facet using the CMOS process, the incompatible in structures between electrical and optical devices would degrade the performance of on-chip optical interconnects.
In this paper, a silicon-on-insulator (SOI)-based optical interconnect transmitter using a silicon-based trapezoidal waveguide with a 45° micro-reflector is demonstrated for the first time. Such a SOI-based optical interconnect transmitter could be adopted in the silicon-based intra-chip optical interconnects using guided-wave optical paths as show in Fig. 1 . In the figure, electronics such as driver ICs and amplifier ICs as well as photonics such as vertical-cavity-surface-emitted-lasers (VCSELs) and photo-detectors (PDs) are flip-chip assembled on the silicon substrate layer of SOI substrate. On the silicon device layer of SOI substrate, a silicon-based trapezoidal waveguide with a 45° micro-reflector is fabricated using the single-step wet-etching process [24, 25]. The proposed waveguide structure forms a three-dimensional optical guided-wave path on the silicon optical bench. Such guided-wave silicon optical bench (GW-SiOB) is intended to connect the transmitting and receiving ports on the silicon substrate layer. An infrared laser beam emitting from the VCSEL chip penetrates into the silicon substrate, impinges upon the Si-based 45° reflector at the transmitting port, deflects into the trapezoidal waveguide, impinges upon the Si-based 45° reflector at the receiving port, and then couples into the PD chip. Three benefits as below would be induced by the proposed structure for intra-chip optical interconnects.
Fig. 1 The sketch of SOI-based intra-chip optical interconnect module with a three-dimensional guided-wave path.
- 1. Adopting such a trapezoidal waveguide with a 45° micro-reflector located on the silicon device layer of SOI substrate would simplify and facilitate the intra-chip interconnect of photonics located on a silicon substrate, even the optical interconnection realized within a very compact region.
- 2. The laser beam propagating in the silicon substrate layer would be well-confined due to a low divergent-angle of laser beam and a high refractive-index of silicon material. The laser beam can be further confined within the trapezoidal waveguide to achieve high-efficiency coupling between two photonics.
- 3. Moreover, electronics such as driver and amplifier ICs not only be assembled on the silicon substrate layer, such electronics can be also realized on the silicon layer using a standard CMOS process. Therefore, the propose configuration has potential to achieve a high-density and high-efficiency intra-chip optical interconnect using a cost-effective mass-production procedure.
2. Design of SOI-based optical interconnect transmitter
The layered configuration of SOI substrate applied to the proposed SOI-based optical interconnect transmitter is shown in Fig. 2(a) . In such a SOI structures, two SiO2 layers with a thickness of 2.1 μm are deposited on the front and rear facets to form the hard mask and isolation layers, respectively. The cross-section of proposed trapezoidal waveguide is schematically illustrated in Fig. 2(b). Its structural parameters are described as below: the upper waveguide width (UL) of 20 μm, the lower waveguide width (DL) of 100 μm, the waveguide height (H) of 40 μm, and the sidewall angle (θ) of 45°, the SiO2 buried oxide (BOX) layer thickness of 2.24 um, and the Si substrate layer thickness of 550 μm. The size of trapezoidal waveguide is set according to the divergent angle of laser beam and the silicon substrate thickness.
Fig. 2 (a) The layered configuration of SOI substrate applied to the proposed SOI-based optical interconnect transmitter. (b) The cross-section of proposed trapezoidal waveguide and its structural parameters.
Figure 3 shows the proposed SOI-based optical interconnect transmitter with a VCSEL chip and a trapezoidal waveguide located on the opposite facets. In this transmitter, a laser beam emitting from the flip-chip assembled VCSEL chip would propagate through SiO2 isolation layer, Si substrate layer, and SiO2 BOX layer sequentially, then the laser beam is coupled into the trapezoidal waveguide via the 45° micro-reflector. Finally, a multimode fiber (MMF) with a diameter of 62.5 μm is located at the output end of proposed waveguide with a separation of 100 μm to receive the output power.
Fig. 3 The proposed SOI-based optical interconnect transmitter with a VCSEL chip and a trapezoidal waveguide located on the opposite facets.
In order to evaluate optical characteristics of the proposed optical interconnect transmitter, such as the optical signal level and the optical alignment tolerance between VCSEL and waveguide, the ray-tracing simulation is applied in the analysis. As mentioned above, the commercial 1310-nm single-mode VCSEL (BX-5G-1310-SM) made by Beam Express for 5-Gbps operation is adopted. The parameters given in the numerical analysis include the laser wavelength of 1310 nm, the laser half divergent-angle of 9°, and the VCSEL emitting-area diameter of 15 μm. The refractive indices of Si and SiO2 are 3.5072 and 1.4468, respectively. The structural parameters of MMF include diameters of core and cladding layers are 62.5 and 125 μm, respectively.
Figure 4(a) -4(e) show the simulated light-propagation and intensity profile evolution in the proposed structure using the ray tracing method. As shown in Fig. 4(a), a Gaussian-distributed light source emitting from a VCSEL chip is coupled into the MMF via the proposed waveguide structure. Figures 4(b)-4(e) show the intensity profile evolution at the emitting area of VCSEL, the 45° micro-reflector facet, in the trapezoidal waveguide, and the facet of MMF, respectively. As compared with the simulated intensity profile shown in Fig. 4(b) and 4(c), most of laser beam impinges upon the 45° micro-reflector due to a small divergent angle and short optical path, and its beam size extends to be 75 μm. Therefore, the laser beam can be deflected by 45° micro-reflector with a low power radiation, and it can be well confined within the trapezoidal waveguide as show in Fig. 4(d). Finally, the laser beam is coupled into the MMF as illustrated in Fig. 4(e). As shown in Fig. 5(a) , the simulated VCSEL-to-waveguide coupling efficiency can reach −1.63 dB and its alignment tolerances of 1-dB power variation are ± 20 and ± 12 μm, respectively, at the lateral (X- and Z-) directions. As shown in Fig. 5(b), the simulated waveguide-to-MMF coupling efficiency can reach −2.65 dB and its alignment tolerances of 1-dB power variation are ± 21 and ± 16 μm, respectively, at the lateral (X- and Y-) directions.
Fig. 4 The simulated light-propagation and its intensity profile evolution in the proposed structure using the ray tracing method. (a) The light propagation along the SOI-based trapezoidal waveguide bend. (b) Intensity profile at the emitting area of VCSEL. (c) Intensity profile at the 45° micro-reflector facet. (d) Intensity profile in the trapezoidal waveguide. (e) Intensity profile in the facet of MMF.
Fig. 5 The simulated alignment tolerances of 1-dB power variation at the lateral directions. (a) VCSEL-to-waveguide alignment tolerance. (b) Waveguide-to-MMF alignment tolerance.
In order to confirm the electrical performance of proposed optical interconnect transmitter, the electrical insertion loss and return loss of high-frequency transmission lines adopted to connect electronics and photonics, i.e. connections of driver-to-VCSEL and PD-to-amplifier, have been studied. The high-frequency transmission lines are design using the 3D full-wave electromagnetic field software, named high frequency structure simulator (HFSS). Figure 6 shows the layout of high-frequency transmission lines located on the Si substrate layer of transmitter. The transmission lines are made of Au metal with its length, width, and thickness of 1360, 40, and 1 μm, respectively. The period of neighbor channels is 250 μm. The resistivity of SOI substrate is 1000-4000 ohm-cm. As show in the inset of Fig. 6, the crisscross-shaped alignment keys nearby the transmission lines are designed for the double-side alignment between VCSEL and waveguide. The simulation results of high-frequency transmission lines including the return loss (S11) and insertion loss (S21) operated at the frequency below 25 GHz are show in Fig. 7 . As illustrated in this figure, the return loss and insertion loss of proposed transmission line are −17.6 and −0.37 dB, respectively, at the frequency of 25 GHz. It means the transmission lines designed on the proposed GW-SiOB can be operated up to 25 GHz. The optical module based on such a GW-SiOB is possible to be operated up to 10 Gbps. Since the VCSEL adopted in the transmitter is operated at 5 Gbps, the simulated return loss S11 and insertion loss S21 of transmission lines operated at the frequencies of 2.5, 7.5, and 12.5 GHz are shown in Table 1 . The simulation results confirm the proposed optical interconnect transmitter can be operated at the data rate of 5 Gbps. Moreover, it can be further extended to be operated at 10 Gbps, if the VCSEL array of 10 Gbps is applied to the module.
Fig. 6 The layout of high-frequency transmission lines for connections of driver-to-VCSEL and PD-to-amplifier. The inset shows the crisscross-shaped alignment keys for VCSEL/PD–to-waveguide alignment.
Fig. 7 The simulation results of high-frequency transmission lines operated at the frequency below 25 GHz. (a) The return loss S11. (b) The insertion loss S21.
Table 1. Simulated Return Loss and Insertion Loss of Proposed Transmission Lines Operated at 5-Gbps Data Rate
3. Realization and characterization of SOI-based optical interconnect transmitter
To realize the SOI-based optical interconnect transmitter as shown in Fig. 3, a GW-SiOB served as an optical engine for the above-mentioned transmitter is developed. The GW-SiOB composed of the silicon-based trapezoidal waveguides with 45° micro-reflectors on the Si device layer as well as the high-frequency transmission lines and Au/Sn solder bumps on the silicon substrate layer are realized using micro-electro mechanical systems (MEMS) processes as shown in Figs. 8 . The silicon-based trapezoidal waveguides with 45° micro-reflectors are fabricated on {110} planes of the orientation-defined (100) silicon device layer by using anisotropic wet etching process in potassium hydroxide (KOH) solution [24].
Fig. 8 (a) The SEM photos of fabricated multi-channel trapezoidal waveguides with micro-reflectors. (b) The ground end surface and sidewalls of trapezoidal waveguide. (c) The fabricated transmission lines with Au/Sn solder bumps. (d) The VCSEL chip flip-chip assembled on the Si device layer.
The fabricated multi-channel trapezoidal waveguides with micro-reflectors are observed using the scanning electron microscopy (SEM) and shown in Fig. 8(a). The ground end surface and sidewalls of trapezoidal waveguide are also demonstrated in the Fig. 8(b). The measured results of fabricated waveguide profile show that the upper width, lower width, and waveguide depth of waveguide are 19, 98, and 39.9 μm, respectively. The sidewall angle is around 45.26°. According to the fabricated results, the measured waveguide dimension matches to the designed one with a structural error less than 5%. After the fabrication of trapezoidal waveguides, the transmission lines with a thickness of 0.9 μm and Au/Sn solder bumps with a thickness of 1.6 μm are fabricated and show in Fig. 8(c). Finally, the VCSEL chip is flip-chip assembled on the Si device layer using Au/Sn eutectic solder bumps, as show in the Fig. 8 (d).
In order to study the optical coupling efficiency and alignment tolerances of the 62.5-μm-core MMF to the trapezoidal waveguide fabricated on the GW-SiOB, the flip-chip assembled VCSEL chip is turned on at the driving current of 10 mA and deflected the laser beam into the trapezoidal waveguide. At the output part of the proposed waveguide, an infrared (IR) camera is placed to observe the optical field distribution of the waveguide or the multimode fiber is placed to measure the transmission efficiency and alignment tolerance. According to the measurement results, the waveguide-to-MMF coupling efficiency is −6.24 dB, and its alignment tolerance at 1-dB power variation at the X-direction and Y-direction are ± 12 and ± 10 μm, respectively. As shown in Fig. 9 , the alignment tolerances for 1-dB variation at X-direction and Y-direction include measured and simulated results are revealed. The measured coupling-efficiency and alignment-tolerance at X-direction are lower than the simulated values. It results in the misalignment between the VCSEL chip and the trapezoidal waveguide during the double-side alignment for the transmission-line fabrication. The VCSEL-to-waveguide misalignment is measured as about 10 μm in X and Z directions, respectively. The root cause of misalignment between transmission line and silicon waveguide comes from the focal-length limitation of the double-side aligner. The misalignment could be improved by reducing the thickness of SOI substrate.
Fig. 9 The measured and simulated results of waveguide-to-MMF alignment tolerances for 1-dB variation at (a) X-direction and (b) Y-direction.
In order to confirm the high-frequency performances of proposed optical interconnect transmitter, measurements including the S parameters of transmission lines and the eye-pattern of module are carried out. The measurement results of transmission-line performances including the return loss S11 and insertion loss S21 operated at the frequency below 25 GHz are show in Fig. 10 and compared with the simulation results. Since the transmitter is operated at 5 Gbps, the measured return loss S11 and insertion loss S21 of transmission lines operated at the frequencies of 2.5, 7.5, and 12.5 GHz are shown in Table 2 . The measured S parameters are close to the simulated ones. To measure the eye-pattern of proposed optical interconnect transmitter, a planar microwave probe is applied to feed the radio-frequency signal via the transmission lines into the VCSEL chip assembled on the GW- SiOB. A MMF placed at the output end of trapezoidal waveguide is adopted to receive the optical signal. The measurement conditions are shown in the Table 3 . Figure 11 shows the optical eye patterns at 5-Gbps data rates with a PRBS pattern of 215-1 as the VCSEL is biased at 15 mA. The eye-pattern characteristics are summarized as Table 4 . According to the measured data and the clear eye patterns, the proposed optical interconnect transmitter can be operated at the data rate at 5 Gbps.
Fig. 10 The measured S parameters of transmission line and compared with the simulated values. (a) The return loss S11. (b) Insertion loss S21.
Table 2. Measured Return Loss and Insertion Loss of Proposed Transmission Lines Operated at 5-Gbps data rate
Table 3. Eye-Pattern Measurement Conditions
Fig. 11 The eye pattern of the SOI-based optical interconnect transmitter operated at the data rate of 5 Gbps.
Table 4. The eye-Pattern Characteristics of SOI-Based Optical Interconnect Transmitter
4. Conclusion
In this paper, a SOI-based optical interconnect transmitter with trapezoidal waveguides and 45° micro-reflectors is demonstrated. The trapezoidal waveguides monolithically integrated with 45° micro-reflectors facilitate a three-dimensional bending for non-coplanar optical interconnects. It would simplify and shrink the intra-chip optical interconnect located on a silicon substrate. The clearly open eye patterns at 5-Gbps data rate verify the proposed GW-SiOB is suitable for intra-chip optical interconnects. As considering to further integrating more optical functions such as filtering, multiplexing and coupling to the proposed GW-SiOB, the proposed trapezoidal waveguides could be redesign using a rib cross-section of 6 × 10 μm2 for the single-mode operation.
Acknowledgments
This work was supported by National Science Council of the Republic of China under grant number 100-2221-E-008-064.
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