1. Introduction

Once dual polarization quadrature phase-shift keying (DP-QPSK) modulation has been proposed by the Optical Internetworking Forum [1] to reach 100 Gbps per channel over existing infrastructure, higher-order quadrature amplitude modulation (e.g., 64-512 QAM) arises now as a promising alternative to further increase capacity while reducing bandwidth requirements [2, 3]. Polarization diversity coherent receiver combines two main parts: i) a polarization diversity circuitry (e.g. polarization beam splitters) and ii) two phase diversity receivers, one per polarization. In this paper we will focus on the second part, i.e. in the phase diversity receiver also called optical downconverter.

The most widely used solution for optical coherent reception is the 90° hybrid downconverter. A cost-efficient implementation, appropriate for commercial applications, is the monolithic integration on Indium Phosphide (InP) of 90° optical hybrid, based on a 2x4 multimode interference structure (MMI), with four photodiodes on the same photonic integrated circuit [3, 4]. Real hardware suffers from different kinds of imbalances which get worse far away from the central wavelength and increase with fabrication-induced process variations. Hardware imbalances introduce two types of distortion on the received in-phase and quadrature (IQ) signal components [5]: linear and nonlinear. A common linear algorithm, carried out in the digital signal processor (DSP), to mitigate non-ideal performance is the Gram-Schmidt orthogonalization procedure (GSOP) [6]. However, GSOP cannot remove non-linear distortion. Therefore stringent fabrication requirements would be necessary to obtain a high performance coherent receiver for higher-order QAM modulations, which would lead to low fabrication yield and a relatively high cost per device.

A promising alternative to overcome these problems is the 120° phase diversity receiver, which has been recently used as a hardware-impairment tolerant wideband receiver at microwave frequencies [7]. The 120° downconverter has been reported several times for optical communications by making use of 3x3 fiber couplers [8, 9]. Recently, authors have proposed [10] a monolithically integrated 120° downconverter based on a 2x3 MMI. This approach makes use of a simple linear calibration strategy to fully correct the receiver imbalances. When compared with the traditional 90° hybrid receiver, the main advantages of the 120° downconverter are higher dynamic range, wider operating bandwidth and relaxed fabrication tolerances. Although these conclusions were stated in [10], the last one was only deduced from the others but not proven, since only optimized nominal designs (i.e. without fabrication errors) were considered. Moreover, the effect of finite resolution of analog-to-digital converters (ADC) placed before the DSP was not taken into account.

In this work the optical front-end modeling is significantly improved, including most of the non-idealities inherent to realistic 90° and 120° integrated downconverters. On one hand, we have studied the effect of realistic fabrication tolerances on InP platforms on the performance of both types of receivers. On the other hand, it has been also analyzed the effect of limited ADC resolution. Simulation results clearly show that fabrication errors, that substantially degrade the 90° receiver performance, can be easily overcome using the 120° downconverter. It is also found that quantization noise caused by ADC limited resolution affects both receivers in the same limited way. This is an important result, since it proves that linear calibration procedure for 120° downconverter is robust enough for practical implementations. In authors' opinion, the analysis performed in this work confirms the superior performance of 120° downconverter architecture and makes it an interesting alternative to traditional 90° hybrids in those applications in which the cost of the additional ADC is not critical (as it will happen in future optical access networks where lower sampling rates will be required as compared with optical backbone networks).

The paper is organized as follows: Section II describes the monolithically integrated optical downconverters and the effect of typical fabrication errors on the behavior of the passive network. Performance of linear DSP algorithms to overcome degrading hardware non-idealities is carried out numerically in Section III. The detrimental effect on each scheme of a limited ADC resolution will be assessed in Section IV. Finally, Section V provides the main conclusions.

2. Monolithic integration of 90° and 120° optical downconverters

Figure 1 shows the block diagrams of the two complex downconverters considered in this work. The typical approach, see Fig. 1(a), is based on a 2x4 MMI device monolithically integrated with four photodiodes followed by differential transimpendance amplifiers (TIA) [4]. Output analog IQ components are then digitized from two ADCs and further corrected in the DSP to get the received symbols. On the other hand, from Fig. 1(b), the proposed 120° downconverter is based on a 2x3 MMI coupler monolithically integrated with three photodiodes followed by TIAs, ADCs and the DSP.

 

Fig. 1 (a) 90° hybrid and (b) 120° downconverters

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The passive components of the receiver are based on InP/InGaAsP rib waveguides (n_InP = 3.18, n_InGaAsP = 3.27) with nominal core thickness H = 1 μm and nominal etch depth D = 0.5 μm. Input and output sections have been designed using monomode interconnection waveguides of width W_g = 2 μm. Radii of curvature have been chosen to be higher than 650 μm to assure negligible bending losses. Waveguide crossings that can be seen at the output section of the 2x4 MMI, form an angle greater than 40° to reduce losses and crosstalk. The geometry of both MMI devices has been optimized to minimize amplitude and phase imbalances at 1550 nm. The nominal widths and lengths of designed MMIs are respectively W_MMI,90° = 25.2 μm, L_MMI,90° = 1379 μm, W_MMI,120° = 18.8 μm, L_MMI,120° = 1034 μm. Adiabatic tapers with a length L_taper = 100 μm are used to adapt, with negligible losses, the interconnection monomode waveguides to the MMI access ports, of width W_p = 4 μm. The tolerance analysis has been performed taking into account the combined effect of the two main deviations that usually occur during the fabrication of InP based photonic integrated circuits: waveguide width errors (δ_W) and etch depth errors (δ_D). Deviations from the nominal core thickness H has not been considered, since epitaxial growth of InGaAsP/InP layers is very accurate. For a properly adjusted fabrication process, width and etch depth errors are quite low (e.g. |δ_W| < 250 nm and |δ_D| < 100 nm) and they do not affect significantly the performance of interconnection waveguides, tapers or crossings. Unfortunately, it can be shown that these errors are high enough to deteriorate the behaviour of MMI devices [11]. We have considered two different non-ideal situations: i) Low fabrication error (δ_W = −150 nm, δ_D = 45nm) and ii) High fabrication error (δ_W = −250 nm, δ_D = 100nm). It is worth to say that a smaller MMI width (δ_W < 0) has the same effect than a greater etch depth (δ_D > 0), because in both cases the confinement of the guided modes is reduced. Therefore, the combined effect of a negative δ_W and a positive δ_D leads to MMI devices with a noticeable reduced effective width. Since it is well known that effective width is the most critical parameter in these devices [12], the performance of both MMIs will be considerably degraded when compared with the nominal design. Accurate electromagnetic (EM) simulation of all the passive parts of the downconverters has been carried out by a combination of different commercial tools, such as FIMMWAVE & FIMMPROP (Photon Design) and BeamPROP & FullWAVE (Rsoft Inc.).

Maximum Amplitude Imbalance (MAI) and Maximum Phase Imbalance (MPI) are used as figures-of-merit to characterize the passive network. They are defined as the maximum deviation from the ideal value of any of the outputs of the downconverter within a frequency band. Table 1 shows MAI and MPI, calculated over the complete C-band, for three different cases: I. Nominal design, II. Low fabrication error and III. High fabrication error. As it is expected from basic MMI theory [12], the 2x3 MMI exhibits a slightly better performance and tolerance to fabrication errors than the 2x4 MMI, despite both are ‘best effort’ designs.

Table 1. Maximum amplitude and phase imbalance in the C-band for 90° hybrid and 120° coupler receiver

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For the system simulations, performed for both the 90° and the 120° cases, the receiver model comprises the passive part, characterized by the previously EM obtained scattering parameters, and the photodiodes which are modeled by an ideal square-law detector with a common-mode rejection ratio (CMRR) of −22 dB and additive shot-noise. Also, it has been considered an external local oscillator (LO) power of 5 dBm and a bit rate of 56 Gbps, enabling 112 Gbps under dual polarization (in this case LO would require an additional 3dB power if it were followed by a beam splitter). Incoming optical signal-to-noise ratio (OSNR) has been adjusted for a BER = 10⁻⁴ in an ideal coherent receiver in absence of internal noise sources (24.3 dB for 64-QAM and 30.2 dB for 256-QAM). We will consider ideal behaviour of TIAs and DSP blocks. More details of the system simulation scenario can be found in [10].

3. Receiver performance evaluation with ideal ADC

In this section it will be shown that, in the absence of ADC quantization noise (ADC resolution has been set to 10-bit which corresponds to an almost quantization noise free situation), the 120° receiver gives a much greater tolerance to fabrication errors than the 90° receiver.

As it was already studied in [5], in a 90° downconverter receiver amplitude and phase imbalances will distort IQ signal constellation due to: i) DC offset ii) rotation and imbalance of the reference axes iii) non-linear error proportional to the signal-to-LO power ratio. The standard procedure to correct the hybrid induced-distortion is the GSOP algorithm [6], which cannot remove the non-linear constellation distortion, and this makes this solution limited for high signal-to-LO power ratios [10]. However, the 120° downconverter was shown to be free from this limitation. Indeed, in this type of receiver, IQ signals can be obtained with negligible distortion by a linear combination of the readings of the three photodiodes (this algorithm is carried out in the DSP), after a simple calibration strategy [10, 13].

In Fig. 2 we study the robustness of proposed architectures (90° hybrid plus GSOP algorithm, versus 120° coupler plus linear calibration) to correct the inevitable imbalances of the receivers due to fabrication tolerances (Cases I, II and III in Table 1). The OSNR penalty (for a BER = 10⁻⁴) in the C-band versus signal power, under higher-order QAM modulation (64-QAM and 256-QAM), is compared for both receivers. It can be seen that the 90° receiver performance is limited by shot-noise and non-linear constellation distortion at low and high signal power levels respectively. These limitations increase for greater fabrication errors finally reducing its dynamic range as manufacturing tolerances are relaxed. In fact, OSNR penalty for 256-QAM reception will be out of the scope of the Fig. 2(b) when fabrication process variations follow Case III. On the contrary, 120° receiver, although also suffering from the same shot noise limitation as the 90° hybrid, is more resistant to non-linear constellation distortion occurring for high signal powers. As a consequence, it is much more resistant to hardware imbalances derived from fabrication tolerances, and it can deal with a worst case fabrication scenario (Case III) with low OSNR penalty. This behaviour can be used beneficially to relax the fabrication tolerances of monolithic receivers, increasing this way the fabrication yield and reducing the overall fabrication cost.

 

Fig. 2 OSNR penalty (for a BER = 10⁻⁴) in the C-band versus signal power in a 90° hybrid (red dashed line) and 120° coupler (black solid line) downconverters as a function of the considered case of fabrication tolerance (Case I/II/III): (a) 64-QAM (b) 256-QAM.

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4. Degradation induced by ADC limited-resolution

Once that it was shown in previous section that the 120° downconverter, with ideal ADCs, can be advantageously used to relax the fabrication tolerances of monolithic coherent downconverters, it is time to study for the first time the effects of ADC resolution on this new type of receiver.

A limited ADC resolution will increase the quantization noise and this will impact on the algorithms to compensate for hardware imbalances in the 90° and the 120° downconverters. Figure 3 shows for both downconverters the OSNR penalty as a function of the ADC resolution when considering fabrication tolerances described by Case III under 64-QAM and Case II under 256-QAM. It can be seen for the 90° downconverter that, as previously reported [14], a low quantization noise penalty (<0.1 dB at BER = 10⁻⁴) can be achieved with an ADC resolution of at least 7 and 8 bits, respectively, for 64-QAM and 256-QAM. This figure also shows that the same penalty is obtained for the 120° downconverter. Thus, despite using different calibration algorithms, this new type of receiver is not more sensible to quantization noise that the classical 90° approach.

 

Fig. 3 OSNR penalty (for a BER = 10⁻⁴) in the C-band versus signal power in a 90° hybrid (red dashed line) and 120° coupler (black solid line) downconverters as a function of the ADC resolution: (a) Case III under 64-QAM and (b) Case II under 256-QAM.

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Furthermore, attending to the OSNR penalty obtained for 64-QAM reception, the results of Fig. 3(a) show that, in a realistic scenario suffering from the combined effects of quantization noise and hardware imbalances encountered in practical monolithic receivers, the 120° downconverter can offer almost 1dB improvement of total OSNR penalty while reducing ADC resolution by one bit. This has been highlighted in Fig. 3(a), where it can be seen that a 6-bit ADC resolution 120° receiver outperforms the 7-bit ADC 90° receiver giving 0.9 dB of OSNR penalty improvement. Similar conclusions can be obtained from Fig. 3(b) for Case II under 256-QAM modulation. As a consequence, it is concluded that the superior correction procedure of the 120° receiver allows relaxing not only the fabrication tolerances but also the ADCs resolution requirements in a realistic scenario.

Finally, to demonstrate that the 120° downconverter continues to offer excellent hardware correction capabilities for high density modulations even under the presence of ADC quantization noise, Fig. 4 shows the results for a 120° receiver in a high fabrication error scenario (Case III) under 256-QAM. Compared with those in Fig. 3(b), it can be seen that OSNR penalty is not degraded and thus the proposed receiver offers a robust strategy to correct high fabrication errors with limited ADC resolution even for high density modulations as 256-QAM. Please notice that results of Fig. 4 cannot be compared with those of the 90° downconverter, because this type of receiver is not able to get the required BER for this scenario.

 

Fig. 4 OSNR penalty (for a BER = 10⁻⁴) in C-band versus signal power in a 120° downconverter as a function of ADC resolution under 256-QAM in a high fabrication error scenario (Case III).

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5. Conclusion

We have exhaustively compared the performance of two monolithically integrated optical downconverters. The first one is a conventional 90° hybrid, whereas the second one is the 120° downconverter recently proposed in [10]. In both cases, passive structures have been designed in InP technology, taking into account typical fabrication errors. Higher-order QAM transmission schemes (e.g. 64-QAM and 256-QAM) have been considered under limited ADC resolution. It has been shown that, in a realistic scenario suffering from the combined effects of fabrication errors and limited ADC resolution, very good results in terms of signal dynamic range and operating bandwidth can be obtained with the new type of receiver. Therefore, it can be concluded that this approach, not only improves the receiver performance, but also allows relaxing fabrication tolerances and ADC resolution requirements, thus improving fabrication yield and offering lower potential costs.