1. Introduction

Electro-Absorption/Optic Modulators (EAM/EOM) encode high-speed electronic signals onto optical signals [1]. They are an integral component in silicon photonic integrated circuits (PICs) for intra-chip (on-chip) and inter-chip optical interconnects for applications in areas such as optical fiber communication in data centers [2,3], photonic neural networks [4], biomedical sensing, and long-range light detection and ranging (LiDAR) [5]. The high demand for modulators with ever-increasing performance has driven a need for efficient designs of EAM in terms of the figure of merits (FOM) factors such as high extinction ratio (ER), low insertion loss (IL), small footprint, and high speed [6]. Different schemes that have been reported for the realization of EAM include high-Q photonic ring resonators [7–9], photonic crystal cavities [10–12], as well as plasmonic and hybrid plasmonic-photonic devices. In plasmonic and hybrid plasmonic-photonic devices [13–18], one common aspect is the existence of the metal contact on top of or in the vicinity of the active modulating region that partially pulls the electro-magnetic field out of the guiding layer. This gives rise to the plasmonic nature of the device wherein energy is transferred to surface plasmon oscillations [19]. This plasmonic nature is beneficial as it facilitates deep sub-wavelength confinement of light and thus increased light-matter interaction (LMI) enabling improved sensitivity to a dynamic layer, a small device footprint, and dense device integration. However, this phenomenon inevitably results in increased ohmic losses even at the device’s off state when no modulation is required as the light should always interact with the metal. While plasmonic modulators are therefore able to achieve strong modulation, small size, and energy-efficient operation, they suffer from being lossy, with insertion loss values in the range of ∼3–10 dB, and in some cases even more [14,16]. Ultimately, this limits the practicality of such devices.

There is a need to explore the potential to reduce the loss associated with plasmonic devices, and one avenue is the plasmon-assisted technique. Recently, a plasmon-assisted modulator based on a metal-insulator-metal (MIM) ring resonator has been demonstrated to show a 6 dB reduction (4x) in insertion loss when compared to a non-resonant push-pull Mach Zehnder (MZ) plasmonic device. In this approach, the plasmonic section is selectively used or bypassed to reduce insertion loss by selectively passing light through the plasmonic section only at the device's off (in resonance) state [20].

Here, we look to transition this approach to a non-resonant device by utilizing free-carrier modulation to generate an epsilon-near-zero (ENZ) layer within an otherwise purely dielectric environment and evaluate the trade-offs in the design technique. In particular, we replace the metal contact typically found in a conventional plasmonic or hybrid plasmonic EAM with a heavily doped layer of ITO (N = 1 × 10²⁰ cm⁻³). However, the base carrier concentration is not sufficient to exhibit a metallic response at the operating wavelength of 1.55 µm under the zero-biasing condition (i.e., off or high-transmission state). Thus, the light experiences non-metallic layers for minimal IL. Modulation is achieved through the application of a bias, which generates an ENZ layer through carrier accumulation and localizes the electric field within the lossy ENZ layer for strong modulation. Using this approach we study the performance of rib, slot, and multi-slot waveguides using realistic material/fabrication constraints as well as non-idealities (e.g., contact voltage drop, dielectric breakdown, carrier accumulation via quantum models). Through the lens of ENZ surface-to-TCO volume ratio, we illustrate the potential for a 4-slot based EAM with an ER of 2.62 dB/µm and IL 0.3 dB/µm operating at ∼1 GHz and a single slot design with ER of 1.4 dB/µm and IL of 0.25 dB/µm operating at ∼20 GHz. Furthermore, our analysis illustrates trade-offs in the performance that must be carefully optimized for a given scenario, and points toward the need to improve the mobilities of conformal ENZ materials to push the frontier of device performance.

2. Device simulation and results

2.1 Transparent conducting oxides as tunable materials

The Transparent Conducting Oxide (TCO) material family includes promising materials such as indium tin oxide (ITO), indium-doped cadmium oxide (In:CdO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO) [21–24]. Especially, ITO has been widely reported due to its features such as wide bandgap (∼3.8 eV), ability to be highly doped (2 to 3 orders to that of the Si) [25], and most importantly the ability to show almost vanishing real part of the permittivity also known as ENZ [26,27]. This ENZ behavior can be described by the well-known Drude equation [28,29]:

 

Fig. 1. (a) 1D schematic of the capacitor structure to extract carrier profile within ITO and p-Si. The oxide has been defined as a “charge conservation” layer. The figure also shows the energy band diagram of the structure at a gate volate of −4.7 V (b) Distribution of gate voltage across various section of capacitor structure. Voltage drop across Oxide, ITO, and p-type Si.

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2.2 Active region materials

Plasmonic EAMs reported in the literature largely make use of metal as the contact to bias the device [16,31,32]. Besides working as contact, the metal also supports a hybrid plasmonic-photonic mode which partially pulls the electromagnetic field (EM) out of the silicon and improves overlap with the dynamic layer [16,32]. Even though this phenomenon is helpful in terms of achieving appreciable ER in the device on-state (i.e., low-transmission state), it incurs an undesirable loss in the device’s off-state. To combat this, our goal is to utilize ENZ as a means to both confine and modulate, but only when modulation is needed. This is realized through a capacitor structure comprising ITO, HfO₂, and p-type Si, see the schematic in Fig. 1(a). The Si has been considered as heavily doped ($p = 1{\; } \times {10^{17}}\; \textrm{c}{\textrm{m}^{ - 3}}$) with a p-type dopant to reduce series resistance [16,31]. Analysis and optimization of the capacitor structure were completed using the Density Gradient (DG) model within the finite element method (COMSOL Multiphysics) to provide more accurate accumulation layer carrier profiles than the semi-classical device model [31,34,35]. Figure 1(a) shows the energy band diagram of the capacitor structure at a gate voltage of −4.7 V. We note that HfO₂ was selected as the dielectric for its balance of high permittivity (∼25) and reasonable breakdown strength along with its ability to form very thin, high-quality conformal coatings, but note other oxides may also be used [36,37]. The thickness of HfO₂ has been set to 5 nm because an increased thickness will require an increased operating voltage (Q = CV) to achieve ENZ, which exceeds common on-chip 5 V rails, and results in increased energy consumption. However, the use of a larger spacer layer would be useful in scenarios where device speed is of utmost importance.

To optimize the capacitor, we seek to reduce the carrier density within the ITO (to minimize off-state loss) while still being able to accumulate sufficient carriers under a bias to achieve ENZ, requiring a peak electron concentration of approximately $6.5{\; } \times {10^{20}}\; \textrm{c}{\textrm{m}^{ - 3}}$ for the ITO film taken herein [16,34]. For different base carrier concentrations within the ITO, we observe how the applied gate voltage required to achieve this ENZ condition is distributed throughout various sections of the device (specific material properties used for the simulations are detailed in Appendix I). Figure 1(b) shows the total voltage applied segmented into the voltage drop across the various sections of the capacitor structure. Considering the contacts, the voltage drop within the ITO is reduced (∼0.44 V) as the carrier concentration is increased due to the improved conductivity. This is beneficial as the voltage across ITO is essentially lost energy in the system. However, this reduction is partially counteracted by the increased voltage drop within Si (∼0.14 V), with increased ITO doping. Finally, a reduction in the voltage drop across the 5 nm HfO₂ is observed with higher concentrations, largely due to the ability to apply a smaller voltage (−4.7 V as compared to −5.53 V) to achieve ENZ. This is key to the successful operation because the typical breakdown voltage of HfO_­2 is 2.5 V per 5 nm (5 MV/cm [34]), requiring carrier concentrations in the ITO > $0.2{\; } \times {10^{20}}\; \textrm{c}{\textrm{m}^{ - 3}}\; $ to achieve ENZ without breakdown in our structure. Further doping of ITO could be employed to reduce the required voltage and move further away from the breakdown, but this will bring the unbiased ENZ condition to a shorter wavelength, resulting in increased off-state loss [6,16,32]. As a result, a base carrier concentration of $1{\; } \times {10^{20}}\; \textrm{c}{\textrm{m}^{ - 3}}$ has been taken for ITO for the subsequent simulations as this lowers the optical loss while keeping the applied voltage below the breakdown of the 5 nm HfO₂.

 

Fig. 2. (a-b) Electron and Hole concentration within ITO and p-type Si as a function of gate voltage. The bulk hole carrier concentration within p-type Si is $1\; \times {10^{17}}\; c{m^{ - 3}}$. (c-d) Real and Imaginary part of permittivity within ITO as a function of gate voltage and ITO thickness.

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Using the optimized carrier concentration, the electron and hole concentration within ITO and p-Si for several gate voltages were extracted as shown in Fig. 2(a,b), illustrating the ability to achieve ENZ conditions within the ITO for an applied bias of −4.7 V. We note that the value of the DG effective mass of electrons in ITO was determined by comparing DG and Schrodinger-Poisson (SP) model (Appendix II) [38,39].

2.3 Device geometry

Given the analysis of the capacitor structure, a carrier concentration of $1{\; } \times {10^{20}}\; \textrm{c}{\textrm{m}^{ - 3}}$ and application of −4.7 V bias is suitable for achieving ENZ within the limits of dielectric breakdown for realistic ITO films with a mobility of 40 cm²/V.s [30]. However, as is clear from Fig. 2(c-d), this manifests in a layer with a minuscule thickness (< 1 nm). As a result, it can be considered as a 2D surface, and the overall ER of the modulator is considered as proportional to the ENZ surface area. On the other hand, as the volume of ITO increases, a higher percentage of the total EM field will traverse the lossy ITO material as compared to low-loss Si and HfO₂, thus increasing IL. Therefore, the key metric of ER/IL can be considered as proportional to the ENZ surface-to-TCO volume ratio (SVR) for a given mode shape. To illustrate this, we compare the performance of a traditional rib waveguide and a slot waveguide, the schematics of which are shown in Fig. 3(a-b). Figure 3(c-d) shows the ER (dB/µm) (black curve) and IL (red curve) incurred for a modulation of 6 dB in the case of a rib and single slot configuration, respectively, versus the rib width and Si-rail width. For simplicity, the 2D analysis for the difference in performance between the rib and slot structure can be expressed by the following overlap integrals of ER and IL as shown in Eqs. (2) and (3):

For ER, the figure considers the normalized overlap between the electric field of the optical mode and the cross-sectional area of the thin ENZ surface, reaching unity when the electric field is entirely confined within the ENZ region. Similarly, the IL can be expressed as the normalized overlap between the electric field of the optical mode and the cross-sectional area of the entire TCO (under the assumption the loss within the Si is negligible). So, the FOM can be expressed as the ratio of Eqs. (2) and (3) as shown in Eq. (4):

 

Fig. 3. Schematic of (a) Rib and (b) Slot configurations of EAM. For single slot, W_Rail varies from 180 nm to 320 nm. For multi-slots, ${\textrm{N}_{\textrm{Pillar}}}$ is the number of Si pillars in the middle of two Si rails.${\; }{\textrm{N}_{\textrm{Pillar}}} = 0$ corresponds to single slot configuration while ${\textrm{N}_{\textrm{Pillar}}} = 1,2,3$ correspond to 2, 3 and 4-slot configurations of EAM. (c-d) ER(dB/µm) (black) and IL for 6 dB modulation (red) for rib and single slot configuration respectively. The slot width is 40 nm.

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Additionally, modification of the electric field spatial distribution may also be used to improve the FOM by confining light near the ENZ region (i.e. confinement). However, since the ENZ region is within the TCO, this action will invariably increase the overlap with the TCO as well. As a result, a simultaneous reduction in the volume of the TCO should be applied. The practical limit to this scaling is due to fabrication limitations and the ability to create many thin, parallel, ENZ surfaces with small volumes within the spatial region of the mode. For the rib, the light remains mostly confined within Si irrespective of the rib width and ITO thickness (time average power flow in the Z direction at 0 V, inset of Fig. 3(c)). While this provides reasonably low IL in dB/µm, the ENZ layer alone is insufficient to extract the electric field from the rib to achieve strong mode overlap and modulation. This results in a low ER in the case of the rib configuration, requiring a longer device to achieve appreciable modulation (e.g. 70.48 µm for 6 dB ER with Si waveguide width of 360 nm).

The slot configuration improves upon this primarily by affecting the spatial confinement of the mode and thereby improving its overlap with the dynamic ENZ layer (time average power flow in the Z direction at 0 V, inset of Fig. 3(d)). However, the gains are minimal if the volume of the TCO remains large (e.g. slot widths > 100 nm), Fig. 4. Thus, a reduction in the volume of the TCO is enforced by reducing the slot width, significantly improving performance by reducing the volume of the TCO while maintaining a strong spatial overlap with the ENZ surface. This scaling is limited by fabrication constraints for lithography and etching. Here, we restrict our slot to an aspect ratio of ∼5:1 [40], thus setting W_slot equal to 40 nm for a silicon layer of 220 nm thickness for all subsequent configurations. A potential fabrication procedure for the proposed device is outlined in Appendix III. In our analysis, unless otherwise stated, we only vary the width of the Si waveguide, rail, and pillar for the rib, single, and multi-slot configurations respectively indicating the fact that the increasing trend of Si content in the device geometry decreases the percentage volumetric content of the TCO.

 

Fig. 4. ER (dB/µm) and IL (dB/µm) for single slot configuration as a function of slot width shows increasing loss with increasing slot width containing ITO. The rail width is fixed and equal to 200 nm for single slot configuration.

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Building from this, the SVR may be pushed higher by inserting more ENZ layers, achieved through a multi-slot waveguide. Figure 5(a) shows the comparison among 2 to 4-slot in terms of ER (dB/µm) and IL assuming a length needed to achieve an ER of 6 dB. The 4-slot configuration having a higher ENZ surface area provides higher ER (2.62 dB/µm) while the respective 6 dB IL remains almost steady (∼0.7 dB). To compare single to multi-slots configurations, we consider the ratio of ER (dB/µm) and IL (dB/µm) as the FOM and select structures that have a real part of the effective mode index equal to 2 to allow for efficient coupling of light to and from a typical Si rib waveguide [41]. In this case, the single slot has a rail width of 220 nm, the 2 to 4 slot structures have Si pillar width of 180 nm, 120 nm, and 100 nm, respectively, and the slot width remains fixed at 40 nm for all structures. Figure 5(b) shows the comparison in terms of the FOM and active ENZ surface area to TCO volume ratio. Here the TCO volume for all structures has been expressed as a percentage of the total device volume to account for the increase in the size of each structure. Our study indicates that increasing the ENZ surface area from single to multi-slots configuration improves performance, where the 4-slot structure has a FOM of 8.73 which is better than previously reported plasmonic and hybrid plasmonic modulators (e.g. 4.51, 7.1) [6,16,31,32,42,43]. The FOM for multi-slot structures can further be improved by increasing overlap between the optical mode and ENZ region through optimizing the geometrical parameters (e.g. by reducing W_Slot, and also the rail and pillar widths). However, this will change the corresponding effective mode index leading to a more challenging optical coupler design [41,44]. The mode profile at 0 V, the effective mode index, and field confinement at device ON and OFF state for the final optimized 4-slot EAM have been presented in Appendix I.

 

Fig. 5. (a) Comparison of multi-slots configurations with respect to ER (dB/µm) and 6 dB IL (b) FOM (ER/IL) as a function of the total ENZ surface area to TCO volume ratio shows improved performance from single to multi-slot configurations.

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While the approach to improve the ER to IL FOM can be optimized through the SVR and confinement approach, it is also inexorably linked to the speed and energy consumption of the device. To investigate this relationship, we estimate the resistance (taking 6 × 10⁻⁴ Ω.cm as the resistivity of ITO valid for a carrier density of 1 × 10²⁰ cm⁻³ [45] and capacitances of the four configurations corresponding to Fig. 5(b). Assuming a need for 6 dB modulation, the resistances ($R = {{\rho L} / A}$) for single and 2 to 4 slots EAMs are 160 Ω, 274 Ω, 410 Ω, and 536 Ω respectively. Similarly, the estimated capacitances ($C = {{({\varepsilon _0}{\varepsilon _r}A)} / d}$) are 235 fF, 254 fF, 273 fF, and 310 fF respectively. Figure 6(a) shows the corresponding RC limited device speed ($f = {1 / {(2\pi RC)}}$) and energy consumption ($U = ({1 / 4})C{V^2}$) and a comparison with other state-of-the-art modulators reported in the literature is presented in Table 2 in Appendix IV. Overall, a greater than 10x reduction in the IL can be seen, when compared to other plasmonic-style designs, while maintaining appreciable ER (6 dB) and size (∼6 µm²). However, the speed and energy consumption of the devices are negatively impacted.

 

Fig. 6. (a) The speed and energy consumption of the slot waveguide designs, illustrating a trade-off in terms of device operation speed and energy consumption. (b) ER and IL and (c) Speed and Energy consumption for 1-slot configuration respectively as a function of the top ITO contact thickness, outlining an approach to mitigate these issues if constraints on IL and driving voltage are relaxed. The 15 nm device was biased at −4.7 V while the other structures were biased at −5.0 V, required to achieve a comparable peak accumulation densities within the slot region. The slot width remains same for all cases.

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This decrease in speed and increase in energy consumption is a result of the increase in resistance and capacitance of the structures which results from the goal to minimize IL, thereby prioritizing a large area and thin ITO layer. This can be mitigated in several ways: 1) by increasing the thickness of the dielectric spacer, 2) by increasing the thickness of the ITO layer, and 3) by increasing the base carrier concentration of the ITO if one relaxes the constraints on the acceptable IL and driving voltages. For example, Fig. 6(b,c) illustrate that by increasing the thickness of the ITO layer for the single slot design, the speed can be increased to 20 GHz while maintaining similar energy consumption if one can tolerate a moderate increase in the IL of the device (1.07 dB IL for a 6 dB modulation depth). We note that the decrease in ER for the thicker films is due to variations in the mode overlap primarily with the ENZ regions on the outermost edges of the waveguide and further optimization could improve this value. Ultimately, it is clear that the typical tradeoff between energy and bandwidth remains [46], and each structure should be optimized for the specific requirements of the application at hand, considering the relative importance of speed, energy consumption, loss, and size. Nonetheless, the TCO-enabled plasmon-assisted approach allows for the realization of a fully solid-state, non-resonant, compact, robust, and low-loss device for integrated photonics.

3. Conclusion

We have numerically investigated multiple configurations of EAMs with the primary goal of side-step plasmonic loss. To do so we have replaced the typical metal contact from the top of the device with heavily doped ITO to reduce the off-state IL to less than 1 dB while including experimentally achievable parameters for our analysis. We have discussed the factors that impose tradeoffs on the device scheme and its performance. Through our analysis, we have highlighted the beneficial aspect of using increased SVR and mode overlap to reduce loss while maintaining modulation depth by comparing a rib, as well as single and multi-slot configurations, realizing a non-resonant 4-slot EAM device that exhibits ER as high as 2.62 dB/µm and IL as low as 0.3 dB/µm, facilitating 6 dB ER with 0.7 dB IL.

While the approach is a viable scheme to realize low-loss plasmon-assisted modulators with sub-dB IL, it does not escape the typical trade-offs [46,47], and it is emphasized that the device must be carefully optimized for the constraints of a given application using experimental parameters to function as intended, something not always done. Without this, exceptional performance can be predicted [48,49], but not realistically achieved. For example, the use of a low-doped ITO layer requires an operation close to the breakdown of the dielectric to achieve sufficient accumulation of carriers to produce the ENZ layer, and the voltage losses within the various layers reduce the overall energy efficiency and speed. However, slight relaxation on the IL metric enables final optimization of parameters such as the layer thickness, enabling a non-resonant single-slot modulator with ER of 1.4 dB/µm, IL of 0.25 dB/µm, in 6.3 µm² with speeds ∼20 GHz and energy consumption of 1.74 pJ/bit. Such compact non-resonant devices are desirable for applications where thermal environments are unpredictable as they avoid power-hungry thermal stabilization [50]. Moreover, unlike other competing techniques, the system is entirely solid-state and CMOS-compatible, enabling integration with existing silicon photonics platforms alongside operation in robust environments. Ultimately, significant leaps in performance of TCO-based EAMs are tied to improved mobility in conformal TCO materials (currently ∼30–40 cm²/V.s) [16,30,34], as this enables improved field enhancement [31] while minimizing off-state IL.

Appendix I

Material parameters for the determination of carrier profile and device optimization are given in Table 1.

Table 1. Material parameters for the semiconductor and optical analysis

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Effective mode indices $({n_{eff}})$ have been found by analyzing each configuration in the FEM eigenmode solver (COMSOL Multiphysics). The corresponding propagation loss (PL) (dB/µm) has been calculated by the following equation [51], $\alpha = 10|{{{\log }_e} - {{(4\pi {\mathop{\rm Im}\nolimits} \{ {n_{eff}}\} )} / \lambda }} |$. The ER (dB/µm) is expressed by the equation:$ER(dB/\mu m) = {\alpha _{ON}} - {\alpha _{OFF}}$ where ${\alpha _{ON}}$ and ${\alpha _{OFF}}$ are propagation loss at a gate voltage of −4.7 V and 0 V respectively. The IL (dB/µm) is equal to the ${\alpha _{OFF}}$. Figure 7(a) shows the mode profile and the effective mode index for the 4-slot EAM at 0 V. The EM field is mostly confined within the ITO slot. Figure 7(b) shows the field confinement at the ITO/HfO₂ interface upon the application of a biasing voltage of −4.7 V. Figure 7(c) shows the cutline view of the $|{{E_x}} |$ component in device ON and OFF states.

 

Fig. 7. (a) Effective mode index and the Ex-component of electric field at 0 V. The dotted closed line highlights interfaces of ITO/HfO₂/p-Si to show (b) Field confinement at the interface of ITO/HfO₂ at −4.7 V. (c) $|{{E_x}} |$ at 0 V and −4.7V.

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Appendix II

Density Gradient (DG) theory provides a generalized form of the conventional Drift-Diffusion theory. While both methods obey electrostatics and current conservation laws, the main difference between them is the way each method treats the equation of states of the electron and hole gases. According to the DG theory, the equation of states of a carrier (electron/hole) gas depends not only on its density but also on its density gradient and the theory does so by including a quantum potential [35]. This theory has been reported as computationally efficient for device simulation that requires quantum confinement [38]. The carrier (electron/hole) profile at thermal equilibrium can be determined by solving partial differential equations that include a linear-gradient coefficient (b_{n or p}) that measures the strength of the gradient effect in the carrier gas. The linear gradient coefficient is inversely proportional to the product of density gradient effective mass (m*_{n or p}) and a dimensionless parameter, r. It has been reported that the usual practice to determine the carrier profile is to fix the value of r while changing the value of m*_{n or p} and compare the results with the same obtained from solving the Schrödinger and Poisson (SP) equations. However, it is also reported that the product of m*_{n or p} and r is almost one under all conditions [38,39]. We further verify this approach for the electrons in ITO by simulating a 1D MOS (Metal/HfO₂/ITO) structure utilizing both DG and SP analysis available in the finite element method (COMSOL Multi-physics, semiconductor module version 5.5). In COMSOL Multi-physics, the value of the parameter, r is by default fixed as equal to 3. So, we set the value $m_n^\ast $ equal to ${{{m_0}} / 3}$ where ${m_0}$ is the rest mass of a free electron. Figure 8 shows the comparison between electron concentrations in ITO predicted by DG and SP for the applied voltages of 0.1 V and 1 V.

 

Fig. 8. Verification of the DG effective mass of electrons in ITO by comparing electron concentrations derived from DG and SP method for two different voltages. The density gradient effective mass has been set as ${{{m_0}} / 3}$ where ${m_0}$ is the rest mass of free electron. For SP method, the effective mass of electron in ITO has been set as $0.35{m_0}$.

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Appendix III

The process would begin with a standard silicon-on-insulator wafer with a 220 nm thick Si device layer and 2–5 µm thick buried oxide. Next, positive tone electron beam lithography resist, such as ZEP or PMMA, would be applied to the sample. The base racetrack waveguide, grating couplers, and rib-to-slot converter will be patterned in a single layer exposure using electron beam lithography, followed by dry etching of Si using the Bosch process (a mixture of C₄F₈:SF₆ gas chemistry) in an inductively coupled plasma (ICP) system [40,54]. In the next step, a thin region of Si can be doped using conventional thermal evaporation doping processes with either liquid or solid dopants (e.g., BN-HT) where resistivities of 1–20 Ω/Sq. can be achieved based on the process conditions [55]. This can be completed across the entire waveguide device as the thin layer with moderate p-doping does not lead to significant propagation losses on the scale of our device. Alternatively, if selective doping is required, a SiO₂ or Si_xN_y hard mask can be deposited and patterned on top of the Si-layer before the doping process. In the next step, conformal growth of 5 nm HfO₂ can be achieved by the Atomic Layer Deposition (ALD) [56,57]. Using a non-critical photolithography exposure, the HfO₂ can be removed from all regions outside the active region by wet etching in ways such as using diluted HF [58], a mixture of HF and formic acid [59], or using diluted phosphoric acid [60]. Similarly, a conformal ITO thin film with resistivity as low as ∼ 6 × 10⁻⁴ Ω.cm can be deposited via atomic layer deposition (ALD) at relatively low optimum temperature (typically ∼200–325°C) and by optimizing the relative number of In₂O₃ and SnO₂ ALD cycles (using cyclopentadienyl indium (InCp) and ozone as the precursors for indium oxide (In₂O₃) while tetrakis(dimethylamino) tin (IV) and hydrogen peroxide as the source for tin oxide (SnO₂)) [45], followed by an aligned electron beam lithography exposure to pattern the ITO active region and contact trace. Wet etching of ITO can be done using a solution of HCL [61]. Finally, metallic contact pads connecting to the p-Si and ITO layers can be added via photolithography and lift-off.

To inject light into the slot, a modified butt-coupling scheme can be used with an inverted tapered section in between the ridge and slot section, the length of which can be optimized (e.g. ∼140 nm) to achieve a reasonable coupling efficiency (e.g. >90%) and propagation loss. However, in scenarios where the real estate is more important, a compact coupling scheme such as standard butt-coupling with optimized parameters (e.g. ridge core width ∼500 nm, slot rail width ∼275 nm, slot gap 50 nm, a zero gap between the ridge and slot section) can be designed for a proper mode match with a moderately increased loss [62]. As an alternative approach, phase matching between a wire and slot mode can also be achieved with the help of a mode transformer to experimentally realize a reasonable coupling efficiency (>90%) [41].

Appendix IV

Table 2. Performance summary of the state-of-the-art modulators reported in the literature

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Funding

National Science Foundation (1808928, ECCS EPMD Program, USA).

Disclosures

The authors declare no competing financial interest.

Data availability

Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.

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