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Abstract
With the rapid development of cloud services, data-center applications and the Internet of Things, short-reach communications have attracted much more attention in recent years. 4-level pulse amplitude modulation (PAM4) is a promising modulation format to provide both high data rate and relatively low cost for short-reach optical interconnects. In this paper, a joint clock recovery and feed-forward equalization algorithm (CR-FFE) is proposed to simultaneously eliminate the inter-symbol interference (ISI) and track large sampling clock offset (SCO) in PAM4 transmission. The algorithm estimates timing error according to the difference between two tap coefficients of fractionally spaced equalizers, thus solving the problem of incompatible prerequisites between clock recovery and channel equalization. A 10GHz directly modulated laser (DML) based 50-Gbit/s PAM4 transmission experiment is implemented to investigate the performance of the proposed algorithm. Experimental results show that the proposed CR-FFE algorithm can resist SCO up to 1000 ppm after 40 km standard single-mode fiber (SSMF) transmission under the 2x10−2 SD-FEC BER threshold, which is dramatically improved comparing with that of 20 ppm in traditional CR cascaded by FFE algorithm.
© 2019 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. Introduction
Driven by the development of big data, cloud services and the Internet of Things, short-reach communications are highly desired for data center interconnects (DCI), optical access, metro applications, and so forth [1]. The intensity modulation with direct detection (IM/DD) is an attractive solution considering low cost and power consumption [2]. Many advanced modulation formats are utilized to reduce the bandwidth requirements for electronic and optical components [3–10], such as four-level pulse amplitude modulation (PAM4), carrierless amplitude and phase modulation (CAP), discrete multi-tone (DMT) and Kramers-Kronig (KK) receiver [11] based quadrature amplitude modulation (QAM). Due to high spectral efficiency and small footprint, PAM4 systems have received much attention in recent years and ratified by IEEE802.3bs for 400Gbps Ethernet transmission [12]. To truly meet the requirements of low cost and power consumption, low-bandwidth components are highly desired in PAM4 transmissions, while the lack of speed of the E/O-components is compensated by using various digital signal processing (DSP) algorithms [13,14]. Numerous research focused on short-reach PAM4 transmission assisted by DSP algorithms has been done over the years [15–21]. The digital equalizers such as feed forward equalizers (FFE) and decision feedback equalizers (DFE) are utilized to compensate the linear impairments [15,16]. To further mitigate nonlinear effects, a Volterra filter (VF) is generally cascaded after linear impairments compensation [17–19]. Meanwhile, machine learning methods such as support vector machine (SVM) and artificial neural network (ANN) have been proposed and investigated to mitigate nonlinear distortion for PAM4 modulation [20,21].
Apart from the linear impairments and nonlinear distortion mentioned above, sampling clock offset induced by the clock mismatch between the transmitter and the receiver can also sharply degrade the performance. Most equalizers based on symbol interval need to be implemented after clock recovery since their effectiveness must depend on synchronized signal [22,23]. Fractionally spaced equalizers have the ability to combat with clock phase offset in small range because the weighted coefficients can change to decide the right position of clock phase. But the effective range of resisting the phase offset is limited by the taps number of equalizers and the algorithm is difficult to operate when SCO exists [24]. Thus, clock recovery algorithms are generally utilized before impairments compensation and equalization. Two major styles of clock recovery techniques are widely applied in optical communications. One is feed-forward clock recovery such as digital filter and square algorithm [25], which is insensitive to channel distortion. In [26], a 112-Gb/s polarization-division-multiplexed (PDM) PAM4 transmission is achieved employing the digital squaring and filter algorithm to control sampling instances. However, feed-forward clock recovery generally requires a high sampling rate and large computational complexity, thus it is imperfect to be implemented in high-speed PAM4 transmission. The other is feedback clock recovery, which uses a feedback loop to adjust the sampling frequency. Considering the requirements of low complexity and low sampling rate, Gardner algorithm [27] is a promising timing error detector (TED) adopted in the feedback loop. The Gardner phase detector is utilized to counteract SCO at the receiver for a 112-Gb/s Nyquist-PAM4 signal [28]. A demonstration of Gardner algorithm is also realized in this paper for comparison. However, most feedback algorithms for clock recovery have low tolerance towards impairments such as chromatic dispersion (CD) and chirp of modulator [29].
In this paper, we propose a joint clock recovery and feed-forward equalization algorithm (CR-FFE), which estimates timing error based on the difference between two tap coefficients of T/2-spaced FFE. The proposed algorithm can eliminate the inter-symbol interference (ISI) induced by linear impairments and track large sampling clock offset simultaneously. The experimental results show that in 50-Gbit/s PAM4 system based on 10G-class DML, CR-FFE can resist SCO up to 1000 ppm after 40 km transmission, which is dramatically improved comparing with that of 20 ppm using traditional CR cascaded by FFE. Note that this work is extended from our previous research presented in [30], and more detailed analysis is conducted here with additional experimental results. The rest of this paper is organized as follows. In Section 2, we introduce the principle of the proposed CR-FFE for simultaneous clock recovery and equalization. In Section 3, after describing the experimental setup, we present extensive results in comparing the BER performance with different algorithms, respectively. After 40 km fiber transmission, only the proposed algorithm can ensure stable performance and achieve error-free transmission using soft-decision (SD) forward error correction (FEC) when SCO reaches 1000 ppm. Finally, the conclusion is drawn in Section 4.
2. Principle
2.1 Traditional CR cascaded by FFE
The structure of traditional CR cascaded by FFE is shown in Fig. 1. The received PAM4 signals are first sent to the clock recovery module to eliminate the timing phase error introduced by SCO, and then delivered into the FFE module to reduce the amplitude error induced by linear impairments. In this scheme, the clock recovery consists of four main components. First of all, a linear interpolator is used to accomplish clock adjustment based on the received asynchronous samples and two control parameters from numerically controlled oscillator (NCO). Then the timing error can be evaluated by a TED using Gardner algorithm with transition selection [31] here. Subsequently, a narrow-band loop filter (LF) is cascaded to reduce output jitters and extract the stable component from timing error. Finally, a NCO is responsible for determining two control parameters, i.e. the base-point index and the fractional interval . Note that the base-point index identifies the signal samples to be sued for linear interpolation and the fractional interval identifies the coefficients of interpolation formula [32].
Fig. 1 The structure of traditional CR cascaded by FFE (r: received signals; x: input signals of FFE; y: output signals of FFE; k: the current moment; 1s: one sample per symbol; 2s: two samples per symbol; TED: timing error detector; LF: loop filter; NCO: numerically controlled oscillator; m: base-point index; u: fractional interval).
After clock recovery, a T/2-spaced FFE is employed to eliminate linear impairments. We initialize the taps of FFE where the center tap is set to one and the rest are set to zero. The tap coefficients are adjusted adaptively by the least-mean-square (LMS) algorithm and two operation modes are used, i.e. Training Mode and Direct Detection (DD) Mode. In the training mode, the reference signal is provided by the training sequence to guarantee convergence. After that, the equalizer can be switched to DD mode. Suppose the number of taps is odd, the output of FFE and the error calculation can be written as:
where and denote the input and output signals of FFE, and are the current moment and tap coefficients, and represent training sequence and the number of samples per symbol, respectively. The number of tap coefficients is labeled as . The error is evaluated by the subtraction between training sequence and output signals in training mode or the difference between input signals and output signals in DD mode.2.2 Proposed CR-FFE
The structure of our proposed CR-FFE is shown in Fig. 2, from which we can observe that the timing error is obtained from the difference between two tap coefficients (noted as and ) of the FFE. The TED output is defined as:
For example, when the sampling occurs late, the larger weighted coefficients would be found after the center tap, thus leading to a negative value of timing error. Otherwise, the value would be positive when the sampling occurs early, as shown in Fig. 3. The modulus value determines the size of adjustment. After that, the estimated timing error is sent to LF and NCO to extract stable component and determine fractional interval successively. Note that the noise bandwidth in LF is an important factor to determine the speed and precision of synchronization, which is optimized and set with the same value in two methods for fair comparison. Finally, the same linear interpolator is employed to adjust the sampling instant.
Fig. 3 The tap weights when (a) sampling occurs late (b) sampling occurs in right position (c) sampling occurs early.
In this scheme, the linear impairments of received signals can be compensated by FFE before the signal access to TED and the resampling signals after CR satisfy the requirements of FFE. The TED can accomplish error estimation more accurately without dispersion and the FFE can complete equalization more efficiently without SCO. Therefore, the mutual cooperation of clock recovery and equalization solves the problem of incompatible prerequisites and makes it possible to complete synchronization and equalization simultaneously by using the proposed CR-FFE.
2.3 Analysis of equalization and clock recovery
To investigate the performance of our proposed CR-FFE, we respectively compare the traditional CR and FFE with the proposed algorithm by simulation. The symbol number of 50-Gbps PAM4 signals is 219 and the results are shown in Fig. 4. The left part depicts the tap weights of conventional FFE and CR-FFE after 20 km transmission during variable SCO, while the right part illustrates a portion of the fractional interval using different scheme after 2km and 20km transmission when SCO is 1000 ppm. Note that all tap coefficients are obtained after the equalization is completed and the SCO is generated in simulation by resampling the digital signals (such as 2.0002 samples per symbol corresponding to 100 ppm).The tap lengths of FFE and CR-FFE are both set to 11.
Fig. 4 The tap weights of FFE and CR-FFE after 20 km transmission where (a) SCO = 0 ppm (b) SCO = 2 ppm (c) SCO = 4 ppm (d) SCO = 6 ppm. A portion of the fractional interval when SCO = 1000 ppm after 2 km transmission (e) with CR and (f) with CR-FFE; and after 20 km transmission (g) with CR and (h) with CR-FFE.
On one hand, the sample point with the largest weighted coefficient is closest to the actual clock phase. The tap coefficients of traditional FFE can be changed to select the right position of clock phase, as indicated in Figs. 4(b) and 4(c) by blue lines. However, the clock phase will accelerate the movement with increased SCO and has slipped out of the range when SCO is 6 ppm as shown in Fig. 4(d). Therefore, the conventional T/2 FFE is unable to resist against SCO.
On the other hand, from Fig. 4(e) we observe that the fractional interval of traditional CR has a steadily varying period per 1000 symbols after 2 km transmission, which indicates that the adjustment is accomplished from 2.002 to 2 samples per symbol. However, as shown in Fig. 4(g), the fractional interval becomes irregular and the synchronization of CR is totally unable to work after 20 km transmission due to its low tolerance to impairments. In more detail, the estimated timing error of TED and actual timing error have an increasing difference caused by dispersion. The clock recovery loop will start to retrack when the deviation accumulates to a critical value.
For our proposed CR-FFE, as depicted by red lines in Fig. 4, the tap weights remain constant and the coefficient of center tap is invariably maximum when SCO varies. Meanwhile, the fractional interval shows that the interpolator shifts two samples in 1000 symbols to achieve recovery from 2.002 samples per symbol to 2 samples per symbol, which indicates that synchronization works well as the increase of transmission distance. The reason for this phenomenon is that the TED in our proposed algorithm can detect clock offset after impairments elimination and the FFE can equalize the dispersion after the removal of timing error. Thus, in the proposed joint scheme, the effects of SCO and channel impairments are simultaneously suppressed due to the effective complementation between clock recovery and equalization.
Next, the comparison of complexity of two methods is investigated. As described in Fig. 2 and Fig. 3, the timing error of CR-FFE is obtained by one times subtraction while the traditional CR algorithm needs additionally one multiplication operation [27]. The complexity of other parts is the same in both methods. Considering the existing multiplications, the proposed CR-FFE has similar or slightly lower computational complexity to the original scheme.
In addition, we study the convergence speed of traditional CR cascaded by FFE and proposed CR-FFE in different conditions, as shown in Fig. 5. The training length of FFE and CR-FFE are both set to 3000. For the conventional algorithm, we can see from Fig. 5(a) that a stable state of timing phase error can be observed when symbol number is about 600. After that, the conventional FFE starts working and the declining of residual amplitude error is completely realized after 700 symbols. In contrast, when the proposed CR-FFE is adopted, the required symbol number decreases dramatically and reaches around 400 as shown in Fig. 5(b). When SCO increases from 0 ppm to 1000 ppm, Fig. 5(c) depicts that the speed of convergence for the traditional scheme is almost identical in back-to-back transmission. However, the number of symbols required to achieve both clock recovery and equalization is slightly increased and a minor jitter for phase error is shown in Fig. 5(d). This phenomenon results from the fact that when there are no SCO and channel impairments, the clock recovery and equalization of CR-FFE can interact on each other to accelerate the convergence process. However, the interaction will lead to oscillation near the optimal value and slow down convergence speed when SCO is large. As can be seen from Figs. 5(e) and 5(f), after 20 km transmission and 1000 ppm SCO, the traditional scheme is unable to converge while the proposed CR-FFE obtains a relatively stable error after about 1000 symbols. It indicates that the interaction between CR and FFE in our proposed scheme can successfully complete synchronization and equalization simultaneously under different conditions. In addition, the residual phase error jitter of proposed CR-FFE reduce significantly comparing with traditional scheme due to the filtering effect of FFE.
Fig. 5 The convergence of (a) traditional CR cascaded by FFE and (b) CR-FFE when SCO = 0 ppm after back-to-back transmission; (c) traditional CR cascaded by FFE and (d) CR-FFE when SCO = 1000 ppm after back-to-back transmission; (e) traditional CR cascaded by FFE and (f) CR-FFE when SCO = 1000 ppm after 20 km transmission.
In general, the proposed algorithm can achieve clock recovery and equalization simultaneously to overcome the shortcoming of the traditional cascaded scheme. Meanwhile, when SCO is small, the convergence speed improves further without increasing computational complexity.
3. Experimental results and discussion
The experimental setup is illustrated in Fig. 6. The 27−1 and 211−1 pseudo random bit sequences (PRBS) are generated by a pulse pattern generator (PPG, Anritsu MP 1800A) and combined by a digital to analog converter (DAC) with 32-GBaud bandwidth to obtain the 50-Gbps PAM4 signals. Afterwards, the DAC output signals are amplified using a 38-GHz RF amplifier and then fed into a 10G-class DML. The central wavelength of the modulated optical signal is 1549.39 nm and the launch power is fixed at 7 dBm. The eye diagrams after DAC and DML are shown in Figs. 6(b) and 6(c) respectively, from which we can observe the tremendous influence of limited bandwidth. After SSMF transmission, the optical signals are attenuated by a variable optical attenuator (VOA). The combination of erbium-doped fiber amplifier (EDFA) and an optical passband filter (OPBF) is used to amplify signals and remove out-of-band noise. Then the signals are detected by a commercial 50-GHz DC coupling PIN PD (Finisar XPDV2120R) without inline trans-impedance amplifier (TIA) and sampled by a real-time digital storage oscilloscope (DSO) (Keysight 93204A) with 80-GSa/s sampling rate and a bandwidth of 32-GHz. Finally, the captured signals are stored in computer and subsequently offline processed in Matlab.
Fig. 6 Experimental setup. The eye diagrams of (a) electrical PAM4 signals and (b) optical PAM4 signals in back-to-back system. PPG: pulse pattern generator, VOA: variable optical attenuator, EDFA: erbium-doped fiber amplifier, OPBF: optical passband filter, DSO: digital storage oscilloscope, PWm: power meter.
In the offline DSP, to investigate the performance of our proposed CR-FFE, three schemes labeled as Scheme I, Scheme II and Scheme III are employed. The digital signal is first resampled to 50GSa/s, to achieve 2 samples per symbol, and then passed through the three schemes separately, i.e. FFE only, traditional CR cascaded by FFE and the proposed CR-FFE. To further improve the performance of received signals, a Volterra nonlinear equalizer (VNLE) is adopted [33], which can remove residual linear impairments and alleviate nonlinearity distortion. Generally, the linear impairments of the system and the self-phase modulation (SPM) of fibers can be successfully compensated by the first and third-order kernels of VNLE, while the second-order kernels are used to eliminate the nonlinearity of devices such as DML and square-law detection of PD. The third order discrete VNLE can be described as
where and are the m-th input and output symbol of the VNLE, respectively. represents the j-th order Volterra kernels and denotes the corresponding memory length. In our experiment, the worst performance was observed with 40-km transmission; therefore, we optimize the VNLE based on a 40 km SSMF scenario and the same parameters of the VNLE are used for different schemes. The optimum memory lengths of three orders kernels are set as , and, respectively. The kernel coefficients are updated by using the LMS algorithm. To simplify the convergence procedure, the kernels of each order are updated at different speeds [34], which can be depicted as a gradient vector . The training length of VNLE is set to 2000 for the completion of convergence. Finally, the BER is calculated using about 250k bits after decision and de-mapping.In order to achieve high performance and low complexity, we investigate the BER after FFE in Scheme I and CR-FFE in Scheme III using a variable number of taps without clock offset, as shown in Fig. 7(a). Here, all transmission scenarios in our experiment are considered when SCO is 0 ppm and ROP is −8dBm. It can be noticed that stable BER performance can be achieved when the number of taps is larger than 21 for back to back (BTB) transmission. When the transmission distance increases to 20km and 30km, the taps number we adopt becomes 31. As for the 40km transmission, the BER floor can be achieved with more taps number and the optimum is 41. The fixed step size is used in FFE for simplification. It should be mentioned that CR-FFE has similar BER performance with FFE as a function of taps number. Therefore, the taps numbers of 21, 21, 31, 31 and 41 are selected in all three DSP schemes for transmission distance increased from 0 to 40 km.
Fig. 7 BER performance as a function of taps number (a) when SCO = 0 ppm and (b) after 20 km transmission under different SCO conditions. (S. I: Scheme I; S. II: Scheme II)
The BER performance versus the number of taps with large SCO is shown in Fig. 7(b). When taps number is less than 61, the FFE without clock recovery is unable to track SCO in excess of 100 ppm and the performance is extremely poor. The reason is that clock phase will slip out of the effective range of equalizer taps when SCO get larger. The robust performance can be obtained with increased taps number, but it is not as good as the performance of CR-FFE due to higher residual error. On the other hand, the BER performance of CR-FFE is identical under different SCO conditions and relatively stable with different taps number, which confirms that the proposed algorithm can work normally to resist clock offset with a small number of taps.
Next, we study the impact of SCO on the performance of different schemes over different transmission distances. The results are summarized in Fig. 8(a) for ROP of −8 dBm. As we can see, the algorithms in Scheme I and Scheme II is unable to counteract large SCO, while the proposed CR-FFE in Scheme III can ensure stable and reliable performance as SCO increased from 0 to 1000 ppm. The error-free transmission is achieved after 30-km using hard decision (HD-FEC) threshold of 3.8x10−3 and after 40-km using SD-FEC threshold of 2x10−2, respectively. From Figs. 8(b) and 8(c), we observe that the two tap coefficients used for TED are essentially equal and the fractional interval has a steady varying process, which indicates that equalization and clock recovery are achieved simultaneously after 40km transmission when SCO reaches 1000 ppm. In addition, the asymmetry of tap coefficients reveals that the proposed CR-FFE can deal with the asymmetrical pulses induced by nonlinear distortion.
Fig. 8 (a) The BER performance vs SCO at ROP = −8 dBm; (b) the tap weights and (c) fractional interval of proposed CR-FFE after 40 km transmission when SCO = 1000 ppm.
In the last part of the experiments, we compare the BER performance over transmission distance for the traditional CR cascaded by FFE in Scheme II and the proposed CR-FFE in Scheme III. The results are plotted in Fig. 9(a), which shows that the achievable BER for two schemes is similar when SCO is 0 ppm. However, the traditional scheme fails after 1000 ppm SCO while the proposed scheme can still work well. The BER performance is enormously enhanced by cascading the VNLE for nonlinear compensation. Especially, from Fig. 9(a), we can observe that the performance is first improved and then reduced along with the increasing of the transmission distance. It can be explained as the interaction between chirp of modulator and fiber chromatic dispersion [35]. In the case of SCO tolerance as shown in Fig. 9(b), the achievable offset tolerance of Scheme II is directly proportional to its BER performance. However, the proposed Scheme III can endure SCO up to 1000 ppm after 40km transmission and higher offset is not investigated due to the limitation of hardware.
Fig. 9 (a) The BER performance vs transmission distance for different schemes. (b) The tolerance of SCO vs transmission distance for different schemes.
4. Conclusion
In this paper, a novel joint clock recovery and impairment equalization algorithm is proposed and investigated in a 10G-class DML based 50-Gbit/s PAM4 transmission system. By employing the proposed algorithm, BER below SD FEC threshold of BER = 2x10−2 is achieved after 40km fiber transmission with sampling clock offset of 1000 ppm. This paper verifies that the proposed algorithm can provide significant system performance improvement for PAM4 transmission without increasing computational complexity, which could be a potential choice for next-generation PAM4 transmission.
Funding
NSFC program 61875019, 61675034, 61875020, 61571067, Fund of State Key Laboratory of IPOC (BUPT), Fundamental Research Funds for the Central Universities.
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