1. Introduction

As the demand for higher performance computing will never ending, larger capacity signal transmission and higher speed signal processing become more and more important. Optical interconnects are believed to have great advantages over copper wires in transmitting a bit across rooms, racks, boards and even chips, because of its lower power consumption and larger bandwidth [1–3]. However, inefficient optic-to-electric (O/E) conversions are still required at memory and processing planes where electrical signal processing hold the dominant position, which may degrade the overall performance of the computing system. Optical signal processing, which can potentially operate at the line rate of optical transmission [4], offers us an alternative way to solve this problem.

Optical logic has been studied extensively as a basic element of optical signal processing. Various signal processing applications such as header recognition, data encryption and decryption [5] can be implemented by using different logic gates. To date, lots of elementary logic functions have been performed based on semiconductor optical amplifier (SOA) [6–9], periodically poled lithium niobate (PPLN) [10, 11], highly nonlinear fiber (HNLF) [12–14] and other nonlinear devices. Among these schemes, reconfigurable optical logic gates are especially important for their flexibility, in analogy with the programmable logic arrays (PLAs) which are of great use in the electrical signal processing system. What’s more, with integrated circuits going to be the mainstream of the future optical signal processing system, components based on silicon [15], silicon nitride [16], chalcogenide [17] or other integrated techniques [18, 19] are highly preferred. So far, the silicon-on-insulator (SOI) platform is still the first choice because of its low cost, high stability and compatibility of optics and electronics. 40 Gb/s exclusive or (XOR) [20] and 10Gb/s multiple-channel XOR [21] for DPSK signals have been realized based on FWM in silicon nanowire. Directed logic (DL) has attracted lots of attentions in the recent years which combines the advantages of electrical control and optical transmission [22, 23]. 0.5 Gb/s and 3 Gb/s DLs which can be reconfigured to perform any logic functions have been demonstrated using silicon micro-ring resonators [24, 25]. Limited by the response time of the electrical driving circuit, the fastest DL until now has a working speed of 12.5Gb/s which can perform the exclusive or (XOR) and exclusive nor (XNOR) operations [26].

In this paper, we propose and experimentally demonstrate a kind of reconfigurable logic gate based on FWM in silicon waveguide with an operating speed of 40 Gb/s. Two groups of complementary OOK signals which are demodulated from four NRZ-DPSK signals are coupled into the silicon waveguide together. The carrier wavelengths of these signals are carefully selected to ensure that a full set of two-input logic minterms can be generated simultaneously. As we know, arbitrary two-input logic gates can be generated based on the combinations of minterms. Our former proposal [27] for reconfigurable logic gates based on SOA can produce only one minterm by one nonlinear device. If we want to generate all the two-input minterms through this system, we need totally eight lasers, two delay interferometers (DIs), four SOAs and more than six fiber couplers, which will be extremely complex. Here, to the best of our knowledge, it is the first time that all the minterms can be realized at the same time using a single nonlinear device. By extracting different minterms from the output of the waveguide, we finally obtain all the two-input logic functions in our experiment. All the temporal waveforms of the corresponding logic functions show the right bit sequences. Furthermore, we propose a conception of optical logic system based on our scheme, which may help to realize more compact and flexible optical PLA in the future.

2. Operation principle and experiment setup

The way of using a DI to demodulate the DPSK signal into a couple of complementary OOK signals has been frequently used in our prior works, which can help improving the reconfigurability of the logic system [9, 12, 27]. As we know, an fixed AND logic can be implemented between two OOK signals through FWM. But if we use a DI first to demodulate the DPSK signals ($A$, $B$), we can obtain different sets of OOK signals (($A$, $B$), ($A$, $\overline{B}$), ($\overline{A}$, $B$), ($\overline{A}$, $\overline{B}$)) when we adjust their carrier wavelengths. Therefore, we are able to get different minterms ($AB$, $A\overline{B}$, $\overline{A}B$, $\overline{A}\overline{B}$) after FWM. However, only one minterm can be obtained through one nonlinear device, which will lead to extremely complex systems if we want to get all the minterms at the same time.

Here, we further optimize our prior method and demodulate the DPSK signals into OOK signals with different wavelengths, which helps us realize all the minterms simultaneously by only one DI and one silicon waveguide. The schematic diagram is shown in Fig. 1(a). Four 40 Gb/s NRZ-DPSK signals with different wavelengths are coupled into the wavelength tunable DI which has a free spectrum range (FSR) of 40 GHz. The DPSK signals with wavelengths of ${\lambda }_1$ and ${\lambda }_2$ carry the same bit sequence which is defined as Sig. A. But the signal at ${\lambda }_1$ is located in one of the valleys of the DI’s transmission spectrum, while the other one at ${\lambda }_2$ aligns with one of the peaks. Thus after the demodulation of DI, the transfer and inverted data patterns will be got at ${\lambda }_1$ and ${\lambda }_2$ separately. The same principle is applied to Sig. B at ${\lambda }_3$ and ${\lambda }_4$. Then the four demodulated signals will be launched together into the silicon waveguide that allows for FWM.

 

Fig. 1 Operation principle of the proposal, (a) generation of complementary signals, (b) a kind of relative wavelength distribution for ideal input signals, (c) relative wavelength distribution for practical input signals.

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Theoretically, any degenerate or nondegenerate FWM will not happen when the pump signals contain a set of the complementary data patterns at the same time. Therefore, two groups and only two groups of two-input minterms (eight idlers in total) can be generated if the wavelengths of pump signals are properly selected, as Fig. 1(b) shows. Eight-channel wavelength division multiplexers (WDMs) with FSRs of 200 GHz are used to multiplex these signals. Unfortunately, due to the imperfect demodulation of DI, there will be small fluctuations in the “0”s of the demodulated signals. Moreover, the noise in the signals may also contribute to the FWM between complementary signals and generate several useless idlers. As a result, the signal wavelengths must be selected carefully to keep all the minterms away from these useless idlers. Figure 1(c) illustrates the optimal relative wavelength distribution of the input signals. Limited by the wavelength range (from 1549.1 nm to 1560.3 nm) of the WDM, only a group of minterms pointed out by the red texts can be extracted without any interference. The minterms characterized with black texts are influenced by the useless idlers or located beyond the C band. And we use the gray texts to point out the useless idlers which are produced by the FWM that contains a set of non-ideal complementary signals.

Figure 2(a) shows the experimental setup. The wavelengths of four wavelength tunable lasers (TLs) are respectively 1549.04 nm (${\lambda }_1$), 1552.41 nm (${\lambda }_2$), 1558.85 nm (${\lambda }_3$) and 1560.62 nm (${\lambda }_4$). The Mach-Zehnder Modulator (MZM) is driven by a 16-bit sequence “0101100101010110” to generate 40 Gb/s NRZ-DPSK signals. After being demodulated by the DI, these signals are separated by the second WDM. Three optical delay lines (ODLs) are used to align different signals. Sig. $B$ and Sig. $\overline{B}$ are generated by introducing 4-bit delays relative to Sig. $A$. The polarization controllers (PCs) are used to adjust the polarization state of the signals to align the TE mode of the waveguide. Two high-power erbium doped fiber amplifiers (HP-EDFAs) and two normal EDFAs are adopted to amplify these signals.

 

Fig. 2 (a) Experiment setup for the 40 Gb/s reconfigurable logic gate and (b) the cross section view of the silicon waveguide. OC: optical coupler, VOA: variable optical attenuator.

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The ridge waveguide used in the experiment is about 2-cm long which is fabricated on the SOI wafer with a top silicon layer of 220 nm and bottom SiO₂ layer of 2 µm, also there is a 3-µm thick SiO2 upper cladding. The ridge is 130-nm thick and 550-nm wide, as shown by the cross section diagram in Fig. 2(b). A propagation loss of about 2 dB/cm and coupling loss of about 4 dB per grating coupler have been measured for the TE polarized signals, thus resulting in a total insertion loss of about 12 dB. The dispersion of the waveguide is normal and calculated to be about −1340 ps/nm/km. After the silicon waveguide, a programmable filter (Waveshaper 1000S) with several rectangular-like filtering channels is used to extract different combinations of minterms. The 3-dB bandwidth of each rectangular-like channel is 150 GHz. Suitable attenuations will be added to every channel to balance the power of the minterms. Then these minterms with different wavelengths will superpose with each other and form specific logic gates. The insertion loss of the waveshaper is about 5dB, therefore, an EDFA is firstly used to amplify the output signals. If not, the power of some minterms will be too low to be amplified by the subsequent EDFA. Actually, a couple of WDMs with large wavelength ranges can also be employed to realize the generation of different logic gates according to Fig. 1(c), as the wavelengths of these minterms are located in different channels of the WDMs. One of the WDMs can be used to extract the minterms into different channels, and the other one can be used to multiplex these minterms again to form different logic gates. Variable optical attenuators (VOAs) can be applied in these channels to adjust the power of minterms. However, limited by our experimental conditions, we don’t have WDMs with so many channels. So we finally use a waveshaper instead.

3. Experiment results and discussions

When signals with high pump power are injected into the silicon waveguide, free carriers will be accumulated and produce index changes which may have significant impact on FWM process, especially for the pump pulses with pulse width in the picosecond regime [15]. So the insertion loss variation of the waveguide is measured at different average power of the demodulated signals to see whether there is a serious free carrier effect. As shown in Fig. 3, the insertion loss grows slowly when the pump power is relatively low, but grows faster with higher input power. There exists a threshold for the carrier effect to be obvious [28]. In this experiment, the nonlinear loss caused by two-photon absorption (TPA) and free-carrier absorption (FCA) doesn’t exceed 2 dB at a maximum input power of 21.2 dBm.

 

Fig. 3 Measured insertion loss of the waveguide when varying the average power of the demodulated signals.

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Figure 4(a) illustrates the temporal waveforms of the demodulated signals before coupling into the silicon waveguide, which are clear and show the correct bit sequence. However, as we have mentioned before, there are still some fluctuations and noise in the “1”s and “0”s due to the quality of the original DPSK signal and the imperfect demodulation of the DI. Therefore, even the FWM that contain the complementary signals can still take place. As we can see from Fig. 4(b), the measured transmission spectrum of the waveguide is shown with the red curve, and the 3-dB coupling bandwidth of the grating coupler is about 45 nm. The input power of Sig. $A$, Sig. $\overline{A}$, Sig. $\overline{B}$ and Sig. $B$ are separately 16.9 dBm, 17.1 dBm, 12.3 dBm and 12.3 dBm before launching into the waveguide. The blue curve represents the spectrum after FWM. All the idlers that can be generated by these four pump signals are included in the figure and some of them superpose with each other, which has been made clear in Fig. 1(c). The idlers marked with red texts represent the minterms we want, while the blue marked ones are influenced by the useless idlers or out of the working bandwidth of the amplifiers. Different power levels of minterms come from the diversity of FWM conversion efficiencies under different wavelength intervals, as well as different coupling efficiency. The 3-dB FWM conversion bandwidth around 1550 nm measured using two continuous wave (CW) lights is about 9 nm.

 

Fig. 4 Measured temporal waveforms and spectra: (a) waveforms of demodulated signals before coupling into the silicon waveguide, (b) transmission spectrum of the silicon waveguide (red curve) and optical spectrum after silicon waveguide (blue curve).

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The waveforms of four two-input logic minterms are shown in Fig. 5(a). As marked by the red numbers, all the minterms show the right logic sequences clearly. The amplitude fluctuations in the “0”s and “1”s come from the deviations of the demodulated signals, as we have declared before. Besides, after propagating through the silicon waveguide, almost no relative time delays can be observed among these minterms. The dispersion of our waveguide is about −1340 ps/nm/km, and $AB$ should have a relative time delay of about 0.7 ps compared with $\overline{A}\overline{B}$. Although it is much shorter than the time periods of the signals, it may become a serious problem when longer propagation distance or larger wavelength interval are needed. Waveguide with almost zero dispersion around 1550 nm can be designed to deal with this issue, or additional waveguide with opposite dispersion can also be used to compensate the time delay. The reason why we choose such a kind of ridge waveguide is that we intended to fabricate PIN junction to sweep the free carriers at first. So it is hard to optimize the dispersion to a better value when the thick of top silicon layer and the etch depth are separately fixed to 220 nm and 130 nm. Actually, according to Fig. 3, there is no need to use the PIN junction when we maintain the pump power around 20 dBm. We have calculated the dispersion of the strip waveguides with different widths, as shown in Fig. 6. The thick of top silicon layer is still 220 nm, and it can be easily observed that the dispersion is small and anomalous around a width of 600 nm. Figure 5(b) shows the OSNR of different minterms measured before launching into the CSA. The values of OSNR are relatively lower compared with the prior proposal based on HNLF [12], mainly because of the high insertion loss of silicon waveguide and the low conversion efficiency of FWM. Dispersion management is also critical to solve this problem [29], which can help improving the FWM conversion efficiency around 1550 nm, thus decreasing the pump power and nonlinear loss. Figure 5(c) gives out the waveform of $\overline{A}\overline{B}$ at 1546nm which is interfered by $A\overline{A}$. Compared with $\overline{A}\overline{B}$ at 1565.3 nm, more serious fluctuations in the “0”s can be easily observed. This validates the correctness to arrange the signal with proper wavelengths.

 

Fig. 5 Measured temporal waveforms of minterms: (a) the full set of minterms without any interference, (b) the measured OSNR of the minterms, (c) comparison between $\overline{A}\overline{B}$ at 1546 nm and $\overline{A}\overline{B}$ at 1565.3 nm.

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Fig. 6 Calculated dispersion curve of strip waveguides with different widths (the thick of top silicon layer is 220 nm).

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Figure 7 illustrates all the other logic functions by combining different minterms together. The amplitude jitter in the “1”s mainly comes from the power diversity of different minterms, which can be further improved by finely adjusting the power and has no influence on the correctness of the logic sequences.$A$, $\overline{A}$, $B$, $\overline{B}$, XNOR, XOR are generated from the combination of two minterms. The waveform of XNOR is unique, that the adjacent pulses from $AB$ and $\overline{A}\overline{B}$ superpose with each other and form a NRZ-like data pattern. Actually this is because of the NRZ-DPSK pattern whose rising or falling edges will extend into the adjacent bits after demodulation, which can be avoided if RZ-DPSK pattern is applied. The four maxterms are generated by combining three of the minterms, and the Identity is produced by coupling all the minterms.

 

Fig. 7 Measured temporal waveforms of all the other logic functions by properly combining the minterms.

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All the logic results we obtained show the right bit sequence clearly, which demonstrates that the free carrier effect in the silicon waveguide have little influence on the FWM process when we control the pump power appropriately. In addition, by properly optimizing dispersion of silicon waveguide, the pump power can be further lower down while keeping a relatively high conversion efficiency and obtaining a large conversion bandwidth [29]. Under this condition, the reconfigurable logic gate can substantially operate at higher bit rates, considering the ultrafast response time of kerr nonlinearity. Fully integrated scheme is expected to be implemented in the future, as the technologies of fabricating devices such as DI, array waveguide grating (AWG) and attenuators on a silicon chip are achievable. Besides, SOAs can be added to amplify the signals, relying on the hybrid integration. Or the whole system is able to be realized based on InP/InGaAsP platform, with SOA being the nonlinear medium of FWM.

As we know, compared with electronics, one of the most attractive advantages of optics is that light can propagate in parallel with different wavelengths. In our experiment, we exactly make use of this property which may help to construct a new kind of PLA that is more suitable for optics [12]. As illustrated in Fig. 8(a), we first give out the diagram of electrical standard PLA. If we directly applied this structure to complete the optical PLA, complex coupling circuits should be firstly designed to divide the input signals into different nonlinear devices, which will also bring an extra power dissipation. And then totally four nonlinear devices are required to perform the AND logic function to generate a set of two-input minterms in parallel. These minterms will be coupled with various combinations to realize all kinds of two-input logic functions (Y₀~Y₁₅) at last. As a comparison, the newly proposed optical PLA is shown in Fig. 8(b), by simply doubling the amounts of input channels, only one nonlinear medium is needed while still keeping a parallel output. Just as the working principle in our experiment, an AWG is used to couple the signals into the silicon waveguide to realize the AND logic through FWM. If the demodulated signal quality can be better or the range of wavelength distribution of pump signals can be larger, two sets of minterms can output simultaneously with eight different wavelengths. Then another AWG is used to separate all the outputs. The multi-wavelength feature makes it convenient and flexible for the signals to be separated and combined by the AWGs. Sometimes adjacent channels in AWGs may introduce crosstalk to each other, but when the wavelength intervals are about 1.6 nm for the 40 Gb/s signals, the influence of crosstalk is rather small. As we can see from Fig. 4(b), the minimum OSNR of the effective minterms is about 30 dB and little crosstalk can be observed between adjacent channels. If higher data rate is applied in the future, the wavelength interval must be increased. In addition, as we have mentioned before, the relative time delay among signals with various wavelengths can be decreased by optimized the dispersion of the waveguide. And signals always don’t have to propagate for a long distance in the small signal processing unit. Therefore, by fully utilizing the parallel property of light, the scheme proposed here will contribute to realize more compact and flexible optical PLA.

 

Fig. 8 Schematic diagram for (a) electrical standard PLA; (b) newly proposed optical PLA.

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4. Conclusion

We have proposed and experimentally demonstrated a kind of reconfigurable logic gate based on FWM in silicon waveguide with an operating speed of 40 Gb/s. Thanks to the DI, two groups of complementary signals with different wavelengths can be launched into the waveguide at the same time. By properly setting the relative positions of these signals, a whole set of two-input logic minterms can be extracted simultaneously. Thus all the combinational logic functions can be achieved by combining different minterms. Further efforts should be made to realize higher speed operation, shorter nonlinear medium with lower dispersion, and larger-scale integration.