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We describe a multiwavelength hybrid-integrated solid-state link on a 3 µm silicon-on-insulator (SOI) nanophotonic platform. The link spans three chips and employs germanium-silicon electroabsorption waveguide modulators, silicon transport waveguides, echelle gratings for multiplexing and demultiplexing, and pure germanium waveguide photo-detectors. The 8λ WDM Tx and Rx components are interconnected via a routing “bridge” chip using edge-coupled optical proximity communication. The packaged, retimed digital WDM link is demonstrated at 10 Gb/s and 10−12 BER, with three wavelength channels consuming an on-chip power below 1.5 pJ/bit, excluding the external laser power.
© 2015 Optical Society of America
1. Introduction
Increasing demand for off-chip bandwidth in high performance computing systems has fueled the steady penetration of optical interconnects deep inside the “box”. VCSEL-based mid-board parallel optical modules situated only centimeters from computing or switching payload ICs and operating at data rates up to 25 Gb/s/channel are already breaching the marketplace [1–4]. Owing to its potential for unprecedented energy efficiency as low as 300 fJ/bit and bandwidth density in excess of 1 Tb/s/mm2, wavelength division multiplexed (WDM) silicon photonics is a promising solution to keep pace with projected off-chip IO demands well exceeding 10 Tb/s [5]. An ideal WDM link would be constructed from energy efficient photonic devices, low-power circuits, and low parasitic integration.
Several silicon photonic links, employing monolithic integration of circuits and photonics [5–9] as well as hybrid flip-chip integration [10–13] have been reported on SOI, SOI-CMOS and bulk-Si technology platforms. These include on-chip [7], single interposer [12] as well as fiber-coupled chip-to-chip links [5,8–11,13]. Here we present preliminary results on the first chip-to-chip all-silicon solid-state link. Such links are expected to be an integral part of a macrochip [14] – a logically contiguous piece of densely interconnected silicon that integrates multiple CPUs, memory and an energy-efficient system-wide optical interconnect. Optical proximity communication connects each node (CPU or memory) on the macrochip to a solid-state optical routing layer that supports WDM links between sites using SOI photonic waveguides [Fig. 1]. The low-latency point-to-point interconnect network can enable larger and denser computational nodes exceeding reticule size limits imposed by semiconductor manufacturing.
Specifically, we report on the successful demonstration of an ultralow energy, WDM silicon photonic link [Fig. 2] on a 3 µm SOI photonic platform. The link comprises 5 chips: (1) a WDM transmitter (Tx) chip containing germanium-silicon electroabsorption (EA) Franz Keldysh (FK) waveguide modulators and an echelle grating multiplexer hybrid integrated to a 40 nm bulk CMOS VLSI driver chip; (2) a passive waveguide routing chip; and (3) a WDM receiver (Rx) chip containing an echelle grating demultiplexer and germanium waveguide photo-detectors hybrid integrated to a 40 nm bulk CMOS VLSI receiver chip. The 40 nm VLSI driver and receiver chips are attached to the photonic ICs via Oracle’s ultralow parasitic flip-chip bonding method [15]. The photonic Tx and Rx chips are interconnected to opposite ends of the routing “bridge” chip via edge-coupled polished waveguide facets. An external continuous wave (CW) light source is brought into the link via a pigtailed fiber array on the input side of the Tx chip. This solid-state link may be scaled to increase the number of waveguides as well as the datarate per waveguide and may also be used to create a non-blocking low-latency point-to-point interconnect network between a multitude of chips [14].
Individual link components are described in Sections 2 and 3, followed by link integration and packaging in Section 4. The link test results are presented in Section 5.
2. Photonic components
Each active photonic chip used in the link [Fig. 3(a)-(b)] has three sections: (1) a modulator or photodetector array; (2) a multiplexer or demultiplexer echelle grating; and (3) polished waveguide facets with anti-reflective (AR) coating for Edge-coupled Optical Proximity Communication (EOPxC). The photonic “bridge” chip [Fig. 3(c)] contains only passive waveguides terminated in polished, AR-coated facets for EOPxC. All chips were fabricated in a 6” SOI-photonic foundry using 250 nm stepper lithography technology. The starting wafers have a 3 µm thick SOI layer on a 400 nm thick buried-oxide (BOX) film. The Tx and Rx chips are each 3.75 mm x 14 mm and the bridge chip is 3.75 mm x 12.4 mm. When arranged in an edge-coupled configuration, they yield a 40.4 mm long solid-state link.
2.1 Photonic Tx IC
The photonic Tx IC [Fig. 3(a)] contains a 1x10 array of identical EA modulators based on the FK effect [16–19] feeding into a single echelle grating mux that outputs data on 3 waveguides. Specifically, a horizontal p-i-n GeSi FK modulator with 0.85% Si was used for operation in the 1530-1550 nm wavelength range and for alignment with the mux. The device was 1 µm wide x 40 µm long and was butt-coupled to 3 µm deep Si waveguides [Fig. 4] [17–19]. This geometry allows for low device capacitance and hence, high-speed operation. The latter was also aided by fabrication on high-resistivity SOI substrates. The p and n metal contacts on nine of ten devices are routed to 17 µm square bondpads for hybrid integration while the tenth device has larger pads for probe testing. The measured insertion loss and extinction ratio (3.4dB at 2V, 1550nm) versus reverse-bias voltage, and RF response of representative devices are shown in Fig. 5. FK devices have a wide operating wavelength range (~30 nm) [17] and with a typical band-edge shift of only ~0.8 nm/°C they are tolerant to a wide operating range of temperature [Fig. 6], which eliminates the need for any active wavelength tuning. This is a highly advantageous feature for a photonic link.An echelle grating was used for multiplexing (demultiplexing) on the Tx (Rx) chips. These were designed to the 200GHz ITU grid centered at 195.8 THz [Fig. 7(a)] and to have a free spectral range (FSR) of 40 nm. The echelle mux (demux) is designed to have three outputs (inputs) at a 3 nm spacing. The spectral shift from the mux (demux) can offset temperature effects as well as small Si composition variations allowing selection of an optimal wavelength for higher extinction ratio and lower insertion loss for the modulator. The measured transmission spectrum is shown in Fig. 7 (b). The echelle grating occupies approximately 2 mm2 and has an insertion loss of 2.5 dB. The echelle grating has a temperature dependence of ~0.085 nm/°C while the FK modulator has a temperature dependence of ~0.8 nm/°C. Therefore, in the worst case scenario, the photonic Tx would need to be heated by approximately 30°C to align the best FK working wavelength with the mux.Figure 8 shows the DC performance of the WDM transmitter chip. Transmission loss is normalized to the fiber-to-fiber loss; it includes the fiber-to-chip coupling loss at the input and output, echelle grating loss and FK modulator loss. Power penalty includes the above losses plus the extinction ratio (ER) penalty of the FK modulator and modulation loss.
Fig. 4 (a) Optical image of the fabricated waveguide Franz Keldysh modulator, (b) Device cross-section.
Fig. 5 FK electroabsorption modulator characterization: (a) Insertion loss and extinction ratio vs wavelength and reverse-bias voltages, (b) RF response.
Fig. 7 (a) Mux/demux 200 GHz ITU grid definitions, (b) Spectral response of the fabricated echelle mux/demux.
High-speed measurements of the WDM transmitter chip, prior to hybrid integration, are shown in Fig. 9. The measured device has a 3 dB bandwidth of 20.7 GHz when reverse biased to −2 V. Eye diagrams at 12.5 Gb/s and 25 Gb/s measured at 1544 nm confirm high-speed operation with ER of 3.7 dB and 3.4 dB, respectively.
2.2 Photonic Rx IC
The photonic Rx IC [Fig. 3 (b)] contains a single echelle grating demux, similar to the mux described above, feeding into a 1x10 array of identical horizontal junction p-i-n Ge waveguide photodetectors. The selectively grown Ge is 0.8 µm wide x 10 µm long. These devices have a responsivity of ~1 A/W, a dark current 0.1 μA at −0.5 V, and 3 dB bandwidth ~19 GHz at −0.5 V [Fig. 10]. Figure 11 shows the DC performance of a WDM receiver chip. Responsivity is calculated with the power in the fiber, which includes fiber-to-chip coupling loss and echelle grating loss. Dark current of the 10 channel WDM receiver is < 200 nA at −0.5 V [Fig. 11 (b)]. The receiver has a 3 dB bandwidth of ~19 GHz at −0.5 V and 1541 nm wavelength. Eye diagrams at 12.5 Gb/s and 25 Gb/s confirm high-speed operation of the device [Fig. 12].
2.3 Passive bridge chip
The bridge chip [Fig. 3(c)] connects the output channels of the mux on the Tx chip to the input channels of the demux on the Rx chip. AR-coated etched facet waveguides on the bridge chip accommodate the edge-coupling to Tx and Rx chips.
3. VLSI components
Individual 40 nm bulk CMOS VLSI driver and receiver ICs, flip-chip bonded to the photonic Tx and Rx, respectively, were used in the link. Both chips, shown in Figs. 13 and 14 are approximately 4.5 mm x 5 mm in size; arrays of driver/receiver circuits occupy the northern half of the chip, while supporting circuits and wirebond IOs occupy the southern half. This floorplan enables integration with photonic chips in a diving board configuration with wirebond pads accessible for making connections to the test printed circuit board (PCB).
Fig. 14 (a) Die image of 40 nm CMOS Rx IC, (b) Block diagram of the receiver, showing an adjustable shunt current, an adjustable offset voltage (one of two shown here), and an adjustable clock strobe.
3.1 VLSI Tx IC
The VLSI Tx IC contains 80 transmit circuits arranged in four columns of 20 transmitters each. Each channel can operate up to 12.5 Gb/s and is timed by an external clock at half the datarate. Each transmit circuit/tile contains its own on-chip pseudo-random binary sequence (PRBS) data generator capable of generating 27-1, 215-1 or 231-1 PRBS bit sequences as well as a data inverter to ensure that different transmitters can send independent data streams. This eliminates the need for driving data several mm across the length of the chip using lossy on-chip wires.The transmitter uses a pulsed cascode circuit along the lines of [20]. The load seen by this circuit is dominated by the capacitance of the reverse-biased modulator diode and hybrid bond pads. As the FK device requires a 2 Vp-p (peak-to-peak) modulation signal, a level-shifter circuit that moves the data stream from the normal 0-1 V range to a 0-2 V range is inserted before the transmit circuit [Fig. 13 (b)]. Most of the Tx circuits on the IC are identical with only minor variations for test and characterization purposes. Each circuit is tied to a pair of 17 µm square hybrid bondpads.
3.2 VLSI Rx IC
The Rx IC contains 42 identical receiver circuits arranged in two columns of 16 and one column of 10 receivers in its top-right quadrant. Each channel operates at 10 Gb/s using a half-rate, 5 GHz clock. All receivers are able to drive their CMOS-level output signals into an on-chip PRBS checker for verifying correctness of the received data. Each receiver circuit uses two 25 µm square hybrid bondpads.
The low-power receiver, shown in Fig. 14, consists of a transimpedance amplifier (TIA) to convert the input photodiode current to a voltage, followed by a clocked regenerative sense-amplifier (SA) [21] to restore this signal to full CMOS voltage levels. Four digital-to-analog converters (DACs) are used to set the DLL for appropriate clocking of the SA, to set Iadjust to center the SA input around the voltage threshold, and to set two distinct offset compensation circuits for the two SAs. Digital finite state machines drive and set these four DACs during periodic recalibration of the optical link.
The TIA is a three-inverter chain [21] and is designed for a gain of 4 kΩ at a bandwidth of 7 GHz, assuming an input capacitive load of 60 fF including both photodiode and hybrid bonding pads. This enables operation at −15 dBm input sensitivity with a worst-case ER of 3 dB and a photodiode responsivity of 0.7 A/W, and targeting a signal-to-noise ratio (SNR) sufficient for a bit error rate (BER) of 10−12. An in-depth description of the Tx and Rx ICs and their constituent circuits is available in [21].
4. Hybrid integration and packaging
The complete integration and packaging process flow for the WDM link is illustrated in Fig. 15. First, the individually optimized VLSI and photonic ICs described in the previous sections are hybrid-integrated via a flip-chip bonding process using ultralow parasitic microsolder bumps [15,21–24]. Following this, fiber arrays are attached to the input and output ends of the Tx and Rx, respectively, and the Tx-bridge-Rx assembly is completed via active alignment. The 5-chip link component is then attached to a custom-designed component for mechanical stability and thermal management. Finally, this sub-assembly is die-attached and wirebonded to a test printed circuit board (PCB). A synopsis of these processes is provided below.
The microsolder bump interconnect structure comprises an under-bump-metallization (UBM) layer and a microsolder bump [Fig. 16(a)] [21]. The multilayer UBM, deposited onto both chips in the bond, is a non-oxidizing, diffusion barrier that provides strong interfacial adhesion to the die bondpad and bump. The compliant crown-shaped microsolder bumps sit atop the UBM on the VLSI chips [Fig. 16(b)] and forge a low-resistance connection between chips under thermocompression loading. Chip-to-chip interconnection parasitics have a direct impact on energy-efficiency, bandwidth, and receiver sensitivity in hybrid integrated components. Therefore, bumps scaled down to 12 µm square and contributing as low as 15 fF of parasitic capacitance (estimated) were used to meet our link design targets. This parasitic capacitance is as much as an order of magnitude smaller than traditional first-level interconnects [25]. Several process enhancements were implemented to previously reported fabrication methods [21] to enable a wafer-level process and near-perfect yield [Fig. 16(c)]. UBM was deposited via electroless plating at the reticule-scale on the photonic chips.Hybrid integration was achieved via a thermocompression flip-chip bonding process. The chips were assembled in a diving-board configuration where a portion of the VLSI chip containing the IO pads hangs-off the photonic chip edge to allow wirebonding and two ends of the photonic chip extend beyond the VLSI chip to allow access for fiber-attach and EOPxC. A non-conductive adhesive underfill was inserted between the chips with a resulting bondline <2 µm. Figure 17 shows images of a hybrid-integrated WDM Tx and Rx component.Following hybrid integration, the 5-chip link was built-up sequentially in an active alignment station using two 6-axis precision positioning stages. First, an input fiber block was aligned and attached to the edge-waveguides at the input of the Tx hybrid while using the polished waveguides at the output for monitoring. In a similar manner, a fiber block was aligned and attached to the edge-waveguides at the output end of the Rx hybrid. Following this, a bridge chip was aligned and edge attached to the Tx hybrid output using an optical UV-curable adhesive. The edge-coupling waveguides do not use a tapered geometry. As such, optical coupling loss is particularly sensitive to out-of-plane and lateral misalignment; better than +/− 0.5 µm was targeted in these directions To limit the former along with roll and pitch, the chips were attached to a flat glass piece that serves as a reference plane during alignment, and provides mechanical support to the high aspect-ratio (length:thickness = 22:1) photonic chip assembly during adhesive application and curing. The edge-coupling assembly was repeated to align and attach the Rx-hybrid to the Tx-hybrid + bridge component [Fig. 18 (b)].The assembled photonic link was then adhesively attached to a custom-designed mechanical baseplate having a coefficient of thermal expansion (CTE) matched to Si, and this component was mounted onto a test PCB using mechanical fasteners. Compressible thermal pads were used instead of die attach adhesive to mechanically decouple the link component (low-CTE) from the PCB (high-CTE). These choices were made to minimize stress build-up at the edge-coupled optical interfaces in the link. Finally, the VLSI I/O pads were connected to the test board via Al wedge wire bonds. A photograph of the fully assembled and packaged link is shown in Fig. 19. Additional details on integration and packaging are described in [26].
Fig. 16 (a) Schematic of a microsolder bump interconnect, (b) SEM image of a single microsolder bump, (c) array of microsolder bumps fabricated on the VLSI Tx-IC
Fig. 18 (a) Image of edge-coupled optical interface between a bridge chip and a photonic Tx, both of which are attached to a common glass piece. The inset illustrates sub-micron lateral misalignment. (b) Photograph of an assembled WDM photonic link.
To verify integrity of the link prototype during assembly and packaging, optical transmission across the complete link was measured for each channel at every major step. These measurements were made at wavelengths beyond the absorption edge of the photonic devices. Figure 20 plots the normalized average optical power measured at three stages in the process for three separate builds. Taking into account about 5% measurement error in the test setup, the plot indicates that the packaging did not introduce any appreciable effect on optical coupling at the different interfaces.
Fig. 20 Average transmitted optical power measured at various stages of packaging to verify link integrity.
5. Link testing
5.1 Results
The salient test results obtained from the WDM Tx and Rx photonic chips prior to hybrid integration have been detailed in a previous section. Test results of the completed link are summarized herein.
The optical transmission spectra for all the wavelength channels measured on a packaged WDM link demonstration are shown in Fig. 21. This measurement was performed by sweeping the wavelength using a tunable laser source connected to the input fiber ports of the link and measuring the optical output from corresponding output fiber ports after the photodetectors. Although both the photonic chips and the Tx-IC support 10 wavelength channels, the Rx-IC used supports only 8 channels. Hence, measurement results of only 8 channels are shown in Fig. 21, color labeled from CHN2 to CHN9. As the plot indicates, the echelle grating based Mux and DeMux have well-matched wavelength channels with an FSR of about 40 nm, as designed. The mux (/demux) was designed with 3 evenly separated output (/input) ports and as expected, there are three wavelength peaks about 3nm apart for each wavelength channel. The lower magnitude for wavelength channels between 1520 nm to 1540 nm may be attributed to both FK modulator and Ge photodetector absorption in this wavelength range.For high speed testing, both the Tx-IC and the Rx-IC are controlled using two ports of a JTAG controller through a single test PCB. Each Tx channel is driven by its own PRBS data generator using a 231-1 pattern and a shared half-rate external clock from a BERT. Each receiver is driven by a half-rate external clock from the same BERT with adjustable relative delay. On-chip PRBS checkers were used to measure the link fidelity.
Fig. 21 (a) Picture of the FK link demo board on test station, (b) FK WDM link optical transmission spectra.
Results of high speed testing for all the wavelength channels are summarized in Table 1. In this tested unit, 6 of 8 channels worked for high-speed data transmission. Three channels, CHN6, 7 and 8, operated up to 10.02 Gb/s with BER better than 10−12, while CHN3, 5, and 9 worked up to 6 Gb/s. Very little photocurrent was observed on the two remaining channels (CHN2, CHN4).
Table 1. Summary of high-speed performance for the 8L WDM link.
On-chip power consumption of the 6 working channels was obtained by measuring the supply voltage and current difference for all the supplies for the modulator driver circuit and receiver circuit between the channel ON and OFF states. The results are summarized in Table 2. The electrical power consumed by the transmitter includes the dynamic power consumed by the driver + modulator, the absorbed photo-current power of the EA device as well as leakage current power [19]. Similarly, the receiver power includes the dynamic power consumed by the receiver + photodetector and leakage current power. For the three 10Gbps channels – CHN6, 7 and 8, the measured total power consumption are 13.7 mW, 14.6 mW and 14.8 mW, corresponding to a link energy efficiency of 1.37 pJ/bit, 1.46 pJ/bit and 1.48 pJ/bit, respectively. The estimated total power consumption assuming use of energy-efficient single-mode hybrid optical sources on this platform [27] is listed in the last column.
Table 2. Power measurements for all working channels in the link measured at BER of 10−12
5.2 Discussion
Demonstration of uniform channel performance across the link was affected by a couple of factors. During testing it was found that a parasitic fabry perot (FP) cavity was being created by back reflections within the bridge chip resulting in power fluctuation at the receiver due to temperature changes as small as 0.2 K. This was reduced to about 0.5 dB with optimized AR coating on the Tx, Rx, and bridge chips [Fig. 21].
Device polarization dependence was another contributor to power fluctuation at the receiver. While the 3 µm waveguides are largely polarization independent, other devices in the link, especially the echelle grating mux and demux, are not. As standard single mode fibers (SMF) were used in the input fiber pigtail array, the linearly polarized laser light could be in an arbitrary state when coupled into the on-chip waveguides. In-line polarization controllers could be used to minimize transmission polarization dependence but any residual polarization misalignment relative to the TE or TM mode of the waveguide introduces extra power fluctuation at the receiver.
The two effects combined together typically make the total power fluctuation at the receiver about 1dB. As the receiver bias was designed to be constant in-between calibrations, such power fluctuation significantly degrades the “eye” opening margin. In theory, one could increase the input laser power to compensate such degradation but the maximum average power level that the TIA bias circuit can handle is also limited.
6. Conclusion
We have demonstrated a complete digitally-clocked solid-state, macrochip-like (i.e.“fiberless”) WDM photonic link between a hybrid-integrated Tx that employs GeSi FK EA modulators and a hybrid-integrated Rx that employs Ge waveguide photodetectors. The photonic Tx and Rx dies are hybrid integrated to 40 nm CMOS VLSI electronics and also contain polished waveguide facets for chip-to-chip edge coupling. Active alignment and adhesive attachment were used to physically connect the Tx and Rx hybrids through a passive SOI routing bridge chip. Wavelength channels operating at 10 Gb/s and consuming an on-chip power as low as 1.37 pJ/bit at a BER of 10−12 excluding the off-chip laser were measured. Energy efficient single-mode hybrid optical sources in this 3 μm SOI platform have been separately demonstrated with waveguide-coupled wall-plug efficiencies of 9.5% [27]. For a laser power requirement of 3.0 mW, this source, when included, would correspond to 3.16 pJ/bit – or a total link power (including laser) of 4.23 pJ/bit. The total power is currently dominated by the waveguide-coupled wall-plug efficiency of the laser. This is an area of active investigation, with predicted efficiencies of 20% on the horizon for hybrid silicon-assisted lasers.
Acknowledgments
The authors gratefully acknowledge R. Penumatcha of Oracle Systems, Dr J. Mitchell and C. Stephen of Oracle Labs for their support of this project. This research was developed with funding from the Defense Advanced Research Projects Agency (DARPA). The views, opinions, and/or findings contained in this article/presentation are those of the author(s)/presenter(s) and should not be interpreted as representing the official views or policies of the Department of Defense or the U. S. government. Approved for public release. Distribution unlimited.
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