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We present an expanded all-optical programmable logic array (O-PLA) using multi-input and multi-output canonical logic units (CLUs) generation. Based on four-wave mixing (FWM) in highly nonlinear fiber (HNLF), two-input and three-input CLUs are simultaneously achieved in five different channels with an operation speed of 40 Gb/s. Clear temporal waveforms and wide open eye diagrams are successfully observed. The effectiveness of the scheme is validated by extinction ratio and optical signal-to-noise ratio measurements. The computing capacity, defined as the total amount of logic functions achieved by the O-PLA, is discussed in detail. For a three-input O-PLA, the computing capacity of the expanded CLUs-PLA is more than two times as large as that of the standard CLUs-PLA, and this multiple will increase to more than three and a half as the idlers are individually independent.
© 2014 Optical Society of America
1. Introduction
The rising interest of fast and efficient sub-systems for optical computing is leading the research towards the investigation of photonic digital signal processing. Despite optical devices for digital functionalities are still in their early stages, it is proven that photonic processing has the potential to overcome electronic bottleneck in future communication circuits due to their high-speed capability [1–4]. Up to now, various elementary optical logic operations, such as AND, OR, NOT, XOR, XNOR, NAND, NOR, addition/subtraction [5, 6], et al., have been reported using different optical nonlinearities. Among which, logic operations demonstrated by four-wave mixing (FWM) [7], sum frequency generation (SFG) [8] and difference frequency generation (DFG) [9] have been widely investigated since they show the advantages of bit-rate and modulation format independence [10] as well as low amplified spontaneous emission (ASE) noise [11]. Apart from the basic computing operations, optical digital computing circuits with higher reconfigurability and versatility have also been well developed. Qiu et al. demonstrated a 0.5 Gb/s reconfigurable logic array with microring resonator-based optical switches [12], where the data information is carried on the electrical voltage and tunes the resonant wavelength of the microring resonator, realizing directed logic operation. Similar idea has been applied to realize various logic functions in silicon photonics [13, 14], and the operation speed has been improved to 12.5Gb/s recently [15]. Although these methods show great attraction owing to the advantage of large-scale integration potentiality, the speed limitation is difficult to break through since electrical-to-optical conversion is still required in these approaches. On the other hand, in all-optical domain, a programmable logic array (PLA) was designed using the cross-phase modulation (XPM) in semiconductor optical amplifiers (SOAs) [16]. Here, the PLA is composed of SOA-MZI splitters with a tree-configuration, and the performance of the former stage might largely affect that of the latter one. In [17], O-PLA configured with canonical logic units (CLUs), i.e. logic minterms or maxterms, using cross-gain modulation (XGM) in SOAs was proposed. In this program, logic units with different inputs are obtained from different nonlinear devices, and several important logic functions including full-adder, full-subtractor, multiplier, multiplexer, demultiplexer and decoder are exhibited as examples to show that the canonical logic units-based programmable logic array (CLUs-PLA) can be reconfigured to perform different logic functions. Later in [18], the full-adder and full-subtractor are also experimentally demonstrated.
In this letter, we present an expanded CLUs-PLA based on multi-input and multi-output CLUs generation using four-wave mixing (FWM) in a single highly nonlinear fiber (HNLF) with an operation speed of 40 Gb/s. In the experiments, two-input and three-input CLUs are demonstrated in five different channels simultaneously, and the extinction ratios and optical signal-to-noise ratios are measured to show the effectiveness of the scheme. The computing capacity, defined as the total amount of logic functions obtained by the PLA, is also discussed in detail. It is found that for a three-input CLUs-PLA, the computing capacity of the expanded PLA is more than two times as large as that of the standard one. Potentially, the enhancement can be increased to more than three and a half times as the idlers are individually independent. Compared to our previous work [17], the proposed scheme features a simpler system configuration and lower ASE noise accumulation since no concatenating structure is required in this program. The amount of nonlinear devices is also decreased as the logic units can be generated concurrently. Moreover, this FWM-based method enables the possibilities of ultrafast operation speed [19] and monolithic integration [20], which offer the advantages of larger capacity, compactness, increased reliability, and cost reduction.
2. Expanded CLUs-PLA based on multi-input/output CLUs generation
In this section, we present the proposed expanded CLUs-PLA based on multi-input/output CLUs generation. The structure of this section is as follows. Section 2.1 gives a brief review of the standard CLUs-PLA as a comparison. Section 2.2 explains the operational principles of the multi-input/output CLUs generation and the scheme’s advantages are also discussed. Section 2.3 presents the detail of the experimental demonstrations and measured results. Then the proposed expanded CLUs-PLA is introduced in section 2.4 and the computing capacity of both standard and expanded CLUs-PLA are quantitatively analyzed.
2.1 Standard CLUs-PLA
As discussed in our previous work [17], the sum-of-products typed (SOP-typed) CLUs-PLA (schematically shown in Fig. 1) is composed of three stages, i.e. input circuit (generating complementary data patterns), CLU array (an array of logic units generating canonical logic minterms) and coupling array (realizing final user-defined logic function via coupling corresponding CLUs). Different from other reported approaches [12, 21], a programmable OR array is not required for the proposed SOP-typed PLA since the products are canonical minterms. All combinational logic functions can be demonstrated by adding the canonical minterms directly, which largely reduces the complexity and time latency of the system.
For a standard CLUs-PLA, only one CLU can be achieved with one logic unit. For example, when assuming, and are selected as the inputs of a logic unit, only ABC is obtained as shown in Fig. 2. Correspondingly, a CLUs-PLA with a CLU array composed of logic units like this is defined as a standard CLUs-PLA.
2.2 Operational principle of multi-input/output CLUs generation
Figure 3(a) illustrates the operational principle of the multi-input/output CLUs generation process. Here, the input circuit is demonstrated by a 1-bit delay interferometer (DI). The transfer and inverted data patterns are achieved at constructive and destructive outputs, respectively, when the input data signal is DPSK formatted and the carrier wavelength aligns to the peak of DI’s transmission spectra. For three-input CLUs, the complementary data patterns, i.e. , , , , and , are then available for selection as the inputs of logic unit performed by HNLF. Figure 3(b) shows the schematic spectra of CLUs distribution. Thethree pump signals (i.e. ωC, ωB and ωA) are placed with unequal spacing (i.e. ωB-ωC ≠ωA-ωB) to effectively avoid crosstalk induced by high-order FWM and wavelength overlapping, and the wavelength spaces between the pumps are set as multiples of 1.6 nm to ensure the converted components compliant with the ITU grid. Among these generated FWM components, 2ωC-ωA, ωC + ωB-ωA, ωA + ωB-ωC, 2ωA-ωB and 2ωA-ωC effectively acquire and preserve the amplitude information, and corresponds to logic AC, ABC, ABC, AB and AC when A, B and C are chosen as the inputs. Thus, the full sets of two-input and three-input CLUs can be achieved simultaneously by reconfiguring the inputs. In the experiment, some channels are unused as schematically shown by the gray bands in Fig. 3(b) due to the filtering restriction. It should be noted that this issue can be well resolved by employing a WDM with a wider working range and filters with longer central wavelength. From Fig. 3, one can also see that the scheme not only realizes multi-input CLUs simultaneously, but also multicasts some CLUs such as AC and ABC, suggesting an expanded computing capacity of the proposed CLUs-PLA.
Fig. 3 Operational principle of multi-input/output CLUs generation based on FWM, (a) schematic diagram, (b) spectra of CLUs distribution.
2.3 Experimental setup and results
The experimental setup for multi-input/output CLUs generation is shown in Fig. 4. Three return-to-zero differential phase shift keying (RZ-DPSK) signals with a bit rate of 40 Gb/s and a duty cycle of 33% are generated from the transmitter (Tx) by using a 27 – 1 PRBS sequence.
The wavelengths are 1558.66 nm (λA), 1552.06 nm (λB) and 1549.12 nm (λC), respectively. Afterwards, an erbium-doped fiber amplifier (EDFA) is applied to amplify the signals to 14.8 dBm, and the amplified signals are demultiplexed by a WDM with a free-spectral range (FSR) of 1.6 nm and decorrelated via optical delay lines (ODLs). The signals are then launched into the input circuit based on DIs to achieve complementary data patterns, which are selected as the inputs of the following logic unit. After passing through polarization controllers (PCs), each component of the signals is subsequently amplified and attenuated. These pump signals are multiplexed by another WDM and injected into a 1 km dispersion-flattened HNLF. The average power of A, B and C measured before HNLF are 13.99, 15.12 and 10.37 dBm, respectively. The nonlinear coefficient of the HNLF is 10 W−1·km−1 with a zero dispersion wavelength (ZDW) of 1550 nm, dispersion slope of 0.03 ps/(nm2·km) and loss of 1.5 dB/km. Figure 5 shows the spectra measured right after the HNLF, corresponding to the CLUs distribution. It is seen that the CLU components show good agreement with the theory asdepicted in Fig. 3(b). Simultaneous two-input and three-input CLUs are successfully achieved in five different channels, including AC1 (1539.11 nm), ABC1 (1541.34 nm), ABC2 (1561.51 nm), AB (1565.29 nm) and AC2 (1568.54 nm). Note that although only logic AND of transfer patterns are labeled for simplicity in Fig. 3, the whole set of CLUs can be obtained by switching different inputs. At the output of HNLF, a tunable bandpass filter (TBPF) with a 3 dB bandwidth of 3 nm is used to remove the ASE noise and approximately extract the idler contained logic information. Then a 15 dB amplifier is followed to amplify the result, and another 0.8 nm filter is cascaded to extract the final logic result precisely and further remove the noise. Finally, the logic result is amplified by another 15dB EDFA and sent to the communication signal analyzer (CSA) as well as optical spectrum analyzer (OSA), observing the performance of the optimized CLUs at point X.
The temporal waveforms and eye diagrams of the original signals (transfer patterns) and two-input CLUs are illustrated in Figs. 6(a)-6(c), respectively. One can see from Fig. 6 that the logic sequences of CLUs are correct with wide open eyes, and the logic levels of the results can be clearly identified. Note that AC2 is not observed in the experiment because of the limitation of the filter’s tunable range. From Figs. 6(b) and 6(c), one can observe that theamplitude profile of the mixing product is narrower than that of the input signal as shown in Fig. 6(a) because of the (i.e. E3) effect, and to a certain extent, this amplitude cascading leads to a signal power reduction. However, it is noted that the noise power is either reduced simultaneously due to the noise compression effect in the fiber-based FWM process. In specific, the noise contained in the logic low level of the input signals cannot be efficiently involved in the FWM owing to its low power. On the other hand, the noise contained in the logic high level is either suppressed because of the FWM gain-saturation derived by pump depletion. Both these reasons bring a noise compression to the FWM products. Hence, although the eye traces of the FWM products are relatively weaker than those of the original input signals, which is mainly caused by the decreased logic high levels and the uneven inputs, the optical signal-to-noise ratios (OSNRs) might not be significantly reduced. The operation performance can be further improved by optimizing the modulators to generate input signals with higher quality and reducing the ASE noise via appropriate filtering after EDFAs.
Fig. 6 Measured temporal waveforms and eye diagrams, (a) original data patterns, (b) CLUs at 1565.29 nm (channel AB), (c) CLUs at 1539.11 nm (channel AC1).
To quantitatively verify the effectiveness of the program, extinction rations (ERs) and optical signal-to-noise ratios (OSNRs) of different channels are also measured. The ER is measured by CSA and defined as the as the ratio of P (1) and P (0), where P refers to the average power. The OSNR is measured via OSA and it is defined as the ratio of Psignal and Pnoise, where Psignal denotes the peak-to-peak power of the signal while Pnoise is estimated as the mean power value between channels. As shown in Fig. 7, the ERs for AB and AC1 are both over 11 dB, and the OSNRs measured with a resolution of 0.1 nm are over 38 and 39 dB, respectively, suggesting a good performance of the logic results. This good performance partly benefits from the FWM process by which the noise could be suppressed as aforementioned. In addition, this principle can either find application in pulse reshaping technology [22].
Fig. 7 Measured extinction ratios and optical signal-to-noise ratios, (a) CLUs at 1565.29 nm (channel AB), (b) CLUs at 1539.11 nm (channel AC1).
For the three-input CLUs, the experimental results of the temporal waveforms and eye diagrams are shown in Fig. 8. One can see that clear data sequences of logic operations are observed with CSA. In addition, the eye diagrams of the three-input CLUs exhibit a higher quality than those of the two-input ones since there are much less high logic levels in the three-input logic patterns. Similarly, the eye quality can be improved by the previously proposed approaches with which the logic high levels of the inputs are more even. The ER and OSNR measurements of three-input CLUs are also measured as shown in Fig. 9. It is found that ERs of the logic results in both channels are over 12 dB, and the respective OSNRs are over 37 dB and 39 dB. In Fig. 7 and Fig. 9, OSNRs show a variance of different logic results. This can be mainly explained for two reasons. First, although PRBS pattern is used in the experiment, the total numbers of logic high level contained in different logic results are completely different, which indicates a various signal power for different CLUs. Second, to optimize the FWM process, polarization controller on each input component is fine-tuned during the experiment when the input signals are reconfigured. Thus, the average power of mixing products might not be identical every time, which either brings to an OSNR variance. More CLUs with better performance can be achieved by increasing the number of input signals and nonlinear coefficient of the nonlinear media [23].
Fig. 8 Measured temporal waveforms and eye diagrams, (a) CLUs at 1541.34 nm (channel ABC1), (b) CLUs at 1561.51 nm (channel ABC2).
Fig. 9 Measured extinction ratios and optical signal-to-noise ratios, (a) CLUs at 1541.34 nm (channel ABC1), (b) CLUs at 1561.51 nm (channel ABC2).
2.4 Expanded CLUs-PLA and discussion about the computing capacity
In this section, an expanded all-optical CLUs-PLA based on the demonstrated multi-input/output CLUs generation is proposed. Firstly, Fig. 10 shows the configuration and schematic packaged diagrams of a standard three-input CLUs-PLA for a comparison. Here, the input circuits and logic units included in the blue dashed box in Fig. 10(a) can be integrated and packaged in practical applications, as illustrated in Fig. 10(b). Note that in such a standard CLUs-PLA, only one CLU is achieved with one logic unit as discussed in Section 2. Various logic functions could be achieved at the output by configuring the coupling array. However, when incorporating with multi-input/output CLUs, the standard CLUs-PLA can be expanded. As an example, a three-input expanded CLUs-PLA is schematically shown in Fig. 11. Based on the experimental results presented in section 3.2, when reconfiguring theinputs, four two-input CLUs-PLAs can be achieved from channel AB and channel AC1. The coupling arrays of the AB-based and AC1-based PLAs are depicted in blue and gray colors, respectively. The AC1-based CLUs-PLAs are also distinguished by solid and dashed lines. Additionally, two three-input CLUs-PLAs are obtained from channel ABC1 and ABC2, whose coupling arrays are shown in orange and green colors, respectively. Therefore, compared with the standard CLUs-PLA, both type and quantity of the sub-PLA are expended of the proposed approach, which indicates an increased computing capacity defined as the total amount of logic operations can be achieved from the PLA. The computing capacities of the two CLUs-PLAs are then discussed in detail.
For a standard CLUs-PLA as shown in Fig. 10(a), in the coupling array, CLUs with the same logic value are defined as a word line and the complete set of CLUs are defined as a bit line, which are similar to the corresponding concepts of an electronic memory. Consequently, as to an N-input (i.e. input signal number of the input circuits) CLUs-PLA, there are 2N words /CLUs in each bit line. And in each bit line, different logic functions can be achieved when neglecting null and full, where C denotes the combination operation. More specifically, logic functions composed of different words are regarded as different logic operations. For example, and are totally different logic functions. Here, if there are M bit lines from Y1 to YM, the computing capacity of the N-input standard CLUs-PLA is written as
For an expanded CLUs-PLA as shown in Fig. 11(a), since it contains several different kinds of sub-PLAs, two new variables QT and QC are involved to calculate the computing capacity, where QT denotes the number of channels with the same type (i.e. 2-input or 3-input), and QC represents the number of sub-PLAs per channel (i.e. channel ABC1 or ABC2) with that type. In addition, N is replaced by N’ since multi-input CLUs can be obtained simultaneously, and N’ denotes the quantity of the corresponding inputs. Based on the previous derivation, the computing capacity of an N-input expanded CLUs-PLA with M bit lines is expressed by
Referring to Eq. (2) and the experiment, it is found that QT is a variable related to the mixing products’ distribution, which impacts the computing capacity to a large extent. To be more concrete, QT increases as the idlers are distributed more separately, suggesting a higher computing capacity, while it decreases as the idlers are overlapped, indicating fewer independent mixing terms and a lower computing capacity. On the contrary, QC is a relatively stable parameter when the input number of the sub-PLA is fixed. Thus ideally, only when the idlers are individually independent can the computing capacity of the expanded CLUs-PLA reaches the maximum. As to Eq. (1), it can either be regarded as a special expression of Eq. (2) when both QT and QC are equal to one.
Hence, according our experiment, the computing capacities of the three-input standard and expanded CLUs-PLAs can be then respectively written as
Here, AC2-based CLUs are also taken into account in Eq. (4). One can see that with the same bit lines, the computing capacity of the three-input expanded CLUs-PLA is approximately 2.3 times as that of the standard one. Given improved experimental conditions so that the FWM-based idlers are individually independent as discussed previously, the computing capacity of the three-input expanded CLUs-PLA can be further increased toand the multiple can go up to 3.6. In this case, filters with wider tunable range are required to make use of the extra mixing terms, and correspondingly the bit lines either need to be increased to construct more sub-PLAs.3. Conclusion
Expanded all-optical programmable logic array are presented by simultaneous generation of multi-input canonical logic units. The multi-input/output CLUs are experimentally demonstrated via FWM in HNLF at 40 Gb/s. Two-input and three-input CLUs are synchronously obtained in five different channels. The temporal waveforms of the logic results are correct and clear, and the eye diagrams are widely open. The performance of this program is assessed by extinction ratios and optical signal-to-noise ratios, which are over 11 dB and 38 dB for the two-input CLUs, and over 12 dB and 35 dB for the three-input CLUs, respectively. Computing capacity of the CLUs-PLA is also discussed in detail. It is shown that, for a three-input CLUs-PLA, the computing capacity is more than two times as large as that of the standard one, and this multiple can be potentially increased to more than three and a half with improved experimental conditions. Moreover, this FWM-based expanded PLA is capable of providing higher operation speed (i.e. >320Gb/s [24]) and is particularly attractive in terms of silicon photonic integration potential.
Acknowledgments
The authors would like to acknowledge the National Science Fund for Distinguished Young Scholars (No. 61125501), the NSFC Major International Joint Research Project (No. 61320106016), the National Basic Research Program of China (No. 2011CB301704), and the National Natural Science Foundation of China (No. 60901006 and No. 11174096).
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