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A new optoelectronic serial-to-parallel converter (SPC) has been developed to interface 25-Gbps asynchronous optical packets to CMOS circuitry. Other than all previous optoelectronic SPCs that are limited to single-shot operation and hence that can only be used for packet label processing, the SPC presented here can operate repeatedly with a period of as low as 640 ps to perform 1:16 conversion for an entire burst-mode 25-Gbps optical packet. The new SPC adopts a shared-trigger configuration and hence a single device can either convert a single packet or dual packets simultaneously. In this paper, the design and operation of the new SPC is explained after reviewing the fundamentals of performing bit-by-bit serial-to-parallel conversion by using HEMT-arrays and MSM-PDs. The response of the fabricated SPC device is presented and explained, together with the experimental work done to demonstrate 1:16 dual packet conversion at 25 Gbps.
© 2013 Optical Society of America
1. Introduction
Optical packet switching (OPS) is a promising approach [1, 2] to cope with evolving network traffic demands, as it can provide a means to overcome the bottleneck of throughput scalability in current electrical routers [3] that is constrained by serious power issues [4, 5]. Moreover, it can also pave the way to emerging network applications such as intra Data-Center networks [6] and optical mobile networks [7], by allowing the realization of a low-latency packet-based solution. To enable OPS networks, we have prototyped a hybrid optoelectronic router (HOPR) [8], which as the name implies combines optical and electronic technologies together so as to efficiently realize all the functions necessary for router operation. In addition to packet switching and packet-label processing functions, packet buffering is another essential function that is required for packet contention resolution as well as for implementing higher network functions such as packet regeneration [9], multicasting, Quality-of-Service (QoS) provisioning, and format conversion [10].
As illustrated in Fig. 1, our approach to realize an energy-efficient buffer subsystem relies on having a CMOS memory interfaced with low-power devices, namely the serial-to-parallel converters (SPCs) and parallel-to-serial converters (PSCs), to respectively couple the ultra-fast packet bits to and out of the slower CMOS. Coupling the bits to CMOS has been mainly done by using an all-optical SPC that supports ultrafast operation of up to 1 Tb/s [11]. The all-optical SPC is mainly a saturable absorber all-optical switch that adopts a spin polarization scheme, and that also employs an asymmetric Fabry-Perot cavity structure to enhance the device response. Unfortunately the superior performance of the all-optical SPC comes on the expense of having a bulky size that amounts to 70 × 20 × 20 mm3, together with a high cost to produce a complete module. On other hand, optoelectronic SPCs offer a better compact and scalable solution, but as they lack the capability of fast repeated operation, their use has been limited as packet label converters with single-shot operation [12, 13]. Here we present the first optoelectronic SPC that can operate repeatedly with a period of 640 ps to enable full-packet buffering at 25-Gbps with a conversion factor of 1:16. The device is equipped with 2 sets of serial-to-parallel conversion channels; one set at each device side, and by using a shared optical trigger a single SPC chip can simultaneously convert dual packets.
2. The role of new SPC in buffering different packet types
The previously demonstrated HOPR prototype was limited to handling 10-Gbps optical packets with OOK format; however the increasing traffic demand is pushing forward towards the deployment of higher data rates. The optoelectronic SPC presented in this work can help in achieving this goal in different ways, as the device key features of dual-packet-conversion capability and compact size can facilitate its deployment in different conversion scenarios. As shown in Fig. 2(a), a single SPC can be used to convert the ‘I’ and ‘Q’ signals resulting from a decoder unit after receiving a coherent packet, where the packet itself can get regenerated in the CMOS. The train of trigger pulses necessary for full packet buffering is generated by a separate module called the optical clock pulse train generator (OCPTG) [14, 15].
Moreover, as shown in Fig. 2(b), a single SPC can simultaneously perform the conversion of 2 packet parts at different wavelengths, where only 2 SPCs are sufficient to enable the conversion of a 100-Gbps optical packet composed of 4 multiplexed wavelengths. One other possible deployment scenario is illustrated in Fig. 2(c), in which a high data-rate packet is assumed such that the serial-to-parallel scaling factor of 1:16 provided by a single branch of the SPC results in a converted signal with a speed that still exceeds the CMOS capability. To overcome this condition, a 1-bit delayed copy of the same packet can be launched into the other branch of the same SPC, where every 2 bits of the same packet get simultaneously converted with a total scaling factor of 1:32, where the optical triggering sequence of different conversion channels should be similar to the one given in [13].
3. Ultrafast bit-by-bit conversion using HEMT array
Performing ultrafast bit-by-bit serial to parallel conversion based on an array of high electron mobility transistors (HEMTs) is illustrated in Fig. 3(a).In this configuration the optical packet is converted into an electrical signal with a PD, where the PD output is coupled to a transmission line equipped with an array of HEMTs. All the HEMTs are normally off and by applying a proper signal to each HEMT gate it should be opened at the time that corresponds to a specific bit to be converted, with the gate opening duration being narrow enough to allow for the sampling of only a single bit. To enable the conversion of different packets bits, the HEMTs along the transmission line are operated successively with a train of optical trigger pulses. Using an optical pulse source to control the HEMTs allows for fine time precision as well as low time jitter which otherwise would have been difficult to obtain with an electrical pulse source at high repetition rates.
Fig. 3 (a) Schematic illustration for bit-by-bit conversion using HEMT arrays, and (b) the response of a regular stand-alone MSM-PD.
A metal-semiconductor-metal (MSM)-PD [16] has been selected as the device to convert the optical trigger pulse into the electrical pulse that controls the HEMT gate. This is because the MSMPD transient response is not RC time-limited as the device is characterized by a low parasitic capacitance that enables a fast rise-time. Moreover, the MSMPD can be easily integrated with HEMT circuits as both device terminals can be located on the same plane. However the MSMPD cannot be used directly to control the HEMT gate because it is also characterized by a long time response dominated by the slow carriers i.e., holes. Figure 3(b) shows the voltage measured from one MSMPD terminal by applying an optical trigger pulse with different energies, while having the other MSMPD terminal supplied with 3 volts. A set of electrical pulses with fast rise times, long tailing edges and different amplitudes corresponding to different optical pulse energies can be observed.
Different approaches have been proposed to overcome the MSMPD slow carrier response including advanced Epitaxy grown at low temperature [17] and complex geometries [18]. However, to keep the fabrication process without additional complexities, the discharge based approach [16] illustrated in Fig. 4(a) has been introduced. In this approach, the MSMPD is preceded by a simple RC circuit connected to a DC voltage source, while having the other MSMPD terminal connected to the HEMT gate with a set of two resistances Rbias together with a biasing voltage. By applying an optical trigger pulse with sufficient energy to the MSMPD, enough carriers are generated and consequently the MSMPD acts as a low resistance allowing the charge accumulated in the capacitor Cin to get quickly discharged into the resistance Rbias. And by choosing the time constant RinCin to be sufficiently longer than the RbiasCin, a narrow electric pulse can be generated at the HEMT gate due to the quick depletion of the capacitor Cin that would eventually need a long time to get recharged. Figure 4(b) shows the electrical pulses that result from a discharge-based (DB)-MSMPD trigger circuit with different energies of optical trigger pulses. The sharp rise time and narrow pulse width of the resulting electrical pulses confirm their suitability to control the HEMT gate to allow for a bit-by-bit conversion. But in order to be able to re-operate the DB-MSMPD trigger circuit, an enough time should elapse to let Cin get recharged through Rin. The circuit single-shot operation was sufficient to perform serial-to-parallel conversion for packet label bits as the circuit stays idle during the labels inter-arrival times i.e., several 10’s of nanoseconds, however to perform 1:16 serial-to-parallel conversion for a full packet at 25-Gbps, the DB-MSMPD trigger circuit should be repeatedly operated with a period of 640 ps.
Fig. 4 (a) The discharge-based (DB)-MSMPD trigger circuit, and (b) the response of an MSM-PD included in a discharge-based configuration.
4. The structure of new SPC
Other than the essential requirement of having the DB-MSMPD trigger circuit supporting fast repeated operation, some other demands have to be fulfilled in order to realize a reliable full-packet SPC. This includes enabling efficient conversion of the packet sampled bits into output signals with sufficient amplitude and clear extinction between the high and low signal levels, providing a pattern-effect-free response, in addition to increasing the bit count handled by a single device. As explained later on, the design modifications introduced to address all these requirements can be classified into three main directions; a) employing a new serial-to-parallel conversion scheme and optimizing the DB-MSMPD design parameters, b) implementing a new 2-stage HEMT-based inverter-amplifier circuit with enhanced response, and 3) adopting a new shared-trigger configuration to double the bit count with the same number of optical trigger taps. A schematic illustration of the new SPC is shown in Fig. 5(a), where two parallel transmission lines (TL’s) run along the device; each equipped with a set of 16 conversion channels. Every 2 neighboring channels connected to different TL’s share the same DB-MSMPD trigger circuit. Whereas each channel comprises a main HEMT transistor with its gate driven by the DB-MSMPD trigger circuit, and the other 2 terminals; one connected to a given TL and the other equipped with a holding capacitor Chold before being connected to an output inverter amplifier. By having the bits travelling on the 2 TL’s synchronized in time i.e., adjusted in time when coupled to the device, then every 2 bits that simultaneously arrive at the neighboring channels that share the same DB-MSMPD circuit can be converted with the same optical trigger. Along the device length the DB-MSMPD circuits are triggered in turn with a time difference of single bit duration to convert bits successively. When bit conversion from all channels is done, a new triggering sequence is repeated starting from the DB-MSMPD circuit close to the SPC input. As shown in Fig. 5(b) the SPC device is realized as a compact optoelectronic integrated circuit (OEIC) that is monolithically integrated on InP substrate with total dimensions of 1.7 × 4.5 mm2.
5. New operation scheme and device response
Earlier single-shot SPCs operated with the conventional Sample-and-Hold (S&H) conversion scheme. In this scheme the electrical pulse from the DB-MSMPD trigger circuit shortly opens the main HEMT gate to allow sampling a charge corresponding to the electrical bit present on the TL, and the difference in device output for high and low bits is the net change of charge in Chold after amplification. The new scheme adopted in this work is the Discharge-or-Hold (DoH) scheme [13], in which the charge initially present at the holding capacitor is either discharged into the TL in case of a ‘0’ bit or hold without change in case of a ‘1’ bit. In the S&H scheme, the net change of charge in Chold comes from sampling i.e., the difference between the cases of ‘1’ and ‘0’ bits. With increasing the packet operating frequency the net charge gets limited, as the packet bits get narrower and the process of sampling adequate charge gets more difficult. Moreover, the device fast operation relies on HEMT transistors that are characterized by the absence of a gate insulator. Thus the circuit is subject to minute leakage currents, and Chold is not initially free from charge. On other hand, in the DoH scheme, the net change of charge in Chold comes from discharging i.e., the difference between the cases of ‘0’ and ‘1’ bits. From the equivalent circuits of both schemes shown in Fig. 6(a), it can be found that discharging Chold can be done more efficiently than charging it. This is because the electric pulse charging Chold in the S&H scheme is unavoidably dissipating current in the TL equivalent resistance present in parallel with the operating device channel; thus reducing the current supply that charges Chold, whereas in the DoH scheme, the current discharged from Chold has no other directly competing current source. The DoH scheme also relaxes the requirement of a low HEMT equivalent resistance when turned on, which means that the HEMT-controlling pulse can still be sufficient even with an amplitude that is lower than usual.
Fig. 6 (a) The equivalent circuits for the S&H and DoH schemes, respectively, (b) the SPC output for different values of TL voltages, and (c) the SPC output vs. TL voltage for different optical pulse energies.
Different combinations of design parameters at the DB-MSMPD trigger circuit would result in a HEMT-controlling pulse with different conditions. These parameters have been optimized to enable achieving an electrical pulse repeatedly every 640-ps with sufficient amplitude and properly-narrow pulse width. It should also be emphasized that the circuit optimization doesn’t involve requiring Cin to get completely recharged after being depleted. To examine the device response, an optical trigger pulse is applied to a device channel while slowly varying the DC voltage at the associated TL. As designed, the channel response has an inverted output that settles back to the initial value in 640 ps. As shown in Fig. 6(b), increasing the voltage at the TL decreases the ability of the holding capacitor to get discharged and hence the peak voltage from the amplifier output is gradually decreased. For different pulse energies, Fig. 6(c) shows the relation between the change in the output peak-voltage and the TL bias, and the tradeoff between the output voltage swing and the minimum input voltage distinguishing the low and high signal levels can be noticed. Figures 7(a) and 7(b) show the output from an SPC used for label processing and the output from the current full-packet SPC, respectively. Other than the difference in the DB-MSMPD parameters, different HEMT-based amplifier circuits are deployed in these two devices, where a much longer time response can be easily observed for the single-stage amplifier compared to the 2-stage amplifier employed in this work.
6. Full-packet conversion experiment
Figure 8 shows the setup used to experimentally demonstrate dual 1:16 conversion for 25-Gb/s packets. Emulating optical packets after photodetection, a 25-Gb/s electrical packet is generated by the pulse pattern generator (PPG1) and coupled to one TL in the device, whereas the complimentary packet from PPG1 is simultaneously coupled to the other TL. PPG2 is synchronized to PPG1 and used to generate a single electrical pulse for every 16 pulses generated by PPG1. By adjusting the time difference between the output of PPG2 and its complimentary, both signals are used to drive a custom-made gain-switched laser sub-setup; producing a single optical trigger pulse every 640 ps with a Gaussian shape and pulse width of 10-ps FWHM. The optical pulses then undergo amplification with an EDFA to achieve an average pulse energy of 1.2 pJ at the device MSM-PD. The arrival time of optical trigger pulses at each channel is adjusted to match the set of bits to be converted, such that for channel m the packet bits m + 16n are successively converted until the packet ends, with n being a natural number. By applying optical pulses to each channel separately, all 16 channels connected to the same TL are successively measured followed by the other 16 channels connected to the other TL. Each channel output is measured directly on-wafer by using an active probe that is characterized by high impedance and very low parasitic capacitance; and hence no disturbance is induced to the device response.
The packet from PPG1, shown in Fig. 9(a), has a 27-1 PRBS pattern and NRZ format with a length of 82 ns repeated and a guard band of 20 ns. Figure 9(b) shows the output from Ch.A1 as measured i.e., without comparator, and its zoom-in is given in Fig. 9(c). The extinction between the high and low output levels is large enough to get these 2 levels efficiently recognized by an off-chip comparator. The optical trigger is applied even during the guard band resulting in a continuous series of high output bits for more than 20 ns without affecting the following low output; thus emphasizing the device pattern-effect-free operation. Figure 9(d) shows all 16 upper channel outputs after an off-chip comparator where the successive similar-level bits got connected resulting in an NRZ-like waveform that furthermore would be easily coupled to CMOS. Few bits are labeled with their numbers to facilitate following the conversion sequence. By performing a bit-by-bit check, the successful conversion of all packet bits with a factor of 1:16 was confirmed at both device sides.
Fig. 9 (a) the electrical 25-Gb/s packet from PPG1, (b) the packet 1:16 converted bits from ChA1 without comparator, (c) a zoom-in for ChA1 output, and (d) all upper 16 channels outputs after comparator.
7. Conclusion
An optoelectronic serial-to-parallel converter has been developed to interface burst-mode 25-Gbps optical packets to CMOS circuitry. The new SPC has 32-channels in a shared trigger configuration and operates with an average pulse energy of around 1 pJ. A single chip can convert either single or dual packets with a factor of 1:32 or 1:16, respectively. The device exhibits tolerance to the energy of optical trigger pulses, with a tradeoff between the output voltage swing and the minimum input voltage distinguishing the low and high signal levels. Dual 1:16 conversion for 82ns-long packets has been successfully performed. This SPC is a key device that would enable efficient interfacing of colored, coherent and high line-rate asynchronous optical packets to CMOS buffers, and that would thus highly promote the capabilities of our hybrid optoelectronic router.
Acknowledgment
This work is partially supported by the National Institute of Information and Communications Technology (NICT).
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