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We report the integration of a hybrid silicon evanescent waveguide photodetector with a hybrid silicon evanescent optical amplifier. The device operates at 1550 nm with a responsivity of 5.7 A/W and a receiver sensitivity of -17.5 dBm at 2.5 Gb/s. The transition between the passive silicon waveguide and the hybrid waveguide of the amplifier is tapered to increase coupling efficiency and to minimize reflections.
©2007 Optical Society of America
1. Introduction
Silicon photonics research is motivated to utilize the maturity of CMOS processing technology to fabricate low cost photonic and electronic integrated devices. Light detection is one of the major research topics in silicon photonics. Germanium (Ge) and silicon germanium (SiGe) are good detector materials because of their absorption at the 1.3 and 1.5 μm telecommunication wavelengths and their CMOS processing compatibility. Various Ge waveguide photodetectors (WPD) have been demonstrated using epitaxial growth on silicon photonics platform with high quantum efficiencies [1, 2] and have been integrated with CMOS electronics operating at 10 Gb/s [3]. Also, SiGe or engineered Si WPDs are being investigated to overcome the lattice mismatch of Ge photodetectors [4, 5]. On III-V substrates pre-amplified photoreceivers have been demonstrated incorporating optical amplifiers with photodetectors for increased receiver sensitivity [6]. Recently, we demonstrated a WPD structure using III-V quantum wells as an absorbing layer bonded on a silicon waveguide [7], and a hybrid silicon evanescent amplifier [8] as standalone devices. In this paper, we report the integration of a hybrid silicon evanescent amplifier and a hybrid silicon evanescent photodetector on silicon photonics platform. The receiver has an overall responsivity of 5.7 A/W with an amplifier gain of 9.5 dB and a detector quantum efficiency of 50 %. The device shows 0.5 dB saturation at a photocurrent of 25 mA. Bit error rate (BER) measurements for a nonretrun-to-zero (NRZ) 2.5 Gb/s PRBS shows a receiver sensitivity of -17.5 dBm.
2. Device structure and fabrication
Fig. 1. (a). Top view of a hybrid silicon evanescent pre-amplified receiver (b) device cross section of the hybrid amplifier (not in scale) (c) device cross section of the hybrid photodetector
The hybrid silicon evanescent pre-amplified receiver is comprised of a hybrid silicon evanescent amplifier and a hybrid silicon evanescent waveguide photodetector. A bonded structure of AlGaInAs quantum wells and a silicon waveguide forms a hybrid waveguide for the amplifier and the detector as shown in Fig. 1(a). At the transition between the passive silicon waveguide and the hybrid waveguide of the amplifier, the width of the III-V mesa is tapered from 0 μm to 4 μm over a length of 70 μm to increase the coupling efficiency and to minimize reflection. The width from 4 μm to 14 μm is tapered more abruptly over 5 μm since III-V mesas wider than 4 μm do not laterally affect the optical mode. A 7° tilted abrupt junction is used between the passive silicon waveguide and the detector hybrid waveguide.
The same III-V epitaxial structure is used for the amplifier and the detector and the device cross sections of the amplifier and the detector are shown in Fig. 1(b) and Fig. 1(c), respectively. The details of the epitaxial structure of the III-V layers can be found in Ref. 8. The III-V mesa width of the amplifier is 14 μm. The III-V mesa width of the detector is 3 μm at the p cladding layer and 2 μm at the p-type SCH and the quantum well layers to reduce the capacitance of the device. The detector p and n pads are designed to be 100 μm apart from center to center to use a standard GSG RF probe for high speed testing.
Fig. 2. Scanning electron microscope (SEM) image of (a) eight fabricated devices, (b) III-V taper of the amplifier. (c) 3 μm wide III-V mesa of the detector. Images were taken before the p-probe metal deposition.
The silicon waveguide was fabricated with height of 0.7 μm, width of 2 μm, and slab thickness of 0.3 μm on an silicon on insulator (SOI) wafer with a 1 μm thick buried oxide layer. The III-V epitaxial layers are transferred to the patterned SOI wafer through low temperature oxygen plasma assisted wafer bonding at a 300 °C annealing temperature under vacuum for 18 hours. The InP substrate is removed using a mixture of HCl/H2O. The details of silicon waveguide fabrication and wafer bonding process are described in Ref. 8. The III-V back end processing starts with blanket deposition of Pd/Ti/Pd/Au p-contacts. The p metal serves as a hard mask for the III-V mesas. The hard mask is formed by wet etching the top 100 nm Au layer and dry etching the Pd/Ti/Pd metal layer using a Cl2/Ar-based plasma reactive ion etch after lithographic patterning. The III-V mesas are dry etched to the p-type SCH layer using a CH4/H/Ar-based plasma reactive ion etch followed by a subsequent wet etch of the quantum well layers to the n-type layers using H3PO4/H2O2. The wet etch creates an undercut profile of the SCH and QW layers in the detector. This self aligned process between p contacts and the III-V mesa enables efficient current injection to the tapered III-V regions of the amplifier. Ni/Au/Ge/Ni/Au alloy contacts are deposited onto the exposed n-type InP layer 2 μm away from the edge of the III-V mesa. A 4 μm, current channel is formed through proton implantation on the two sides of the p-type mesa of the amplifier. The n-InP layer is selectively dry etched away to expose the silicon input and output waveguides and to electrically isolate the amplifier and detector n layers. A 5 μm thick SU-8 polymer layer is used to minimize the parasitic capacitance between the p-probe pad and the n-type InP layer. This layer also provides mechanical support to the thin n-InP layer overhanging the silicon waveguide air gap in the detector. 3 μm Ti/Au p-probe pads are deposited and the sample is diced with a silicon facet angle of 10°. After the facets are polished, an antireflection coating of Ta2O5 (~5 % reflectivity) is deposited on the silicon waveguide facets. The total length of the amplifier and the detector is 1240 μm and 100 μm, respectively. The amplifier length includes the two 70 μm long III-V tapers. Scanning electron micrograph (SEM) images of the fabricated hybrid photoreceiver in Fig. 2(a) and close-up views of the two different device junctions are shown in Figs. 2(b) and 2(c), respectively. The silicon confinement factor is calculated to be 63 % while the quantum well confinement is calculated to be 4 %.
3. Experiment and results
The device is mounted on a temperature controlled stage set to 15 °C. The light is coupled into a silicon waveguide through a lensed fiber. The angle between the fiber and the normal to the facet is ~25° to maximize the light coupling from the laser source to the 10° angled silicon waveguide facet. The coupling efficiency from the fiber to the input silicon waveguide is estimated to be -5 dB by measuring insertion loss of a passive silicon waveguide of the same dimensions. The input polarization is controlled by a polarization controller.
The quantum efficiency of the photodetector is measured first by launching the light to input 2 [See Fig. 1(a)] and measuring the generated photocurrent with a Keithley 2400 source meter. Figure 3(a) shows the measured quantum efficiency for TE polarization at 1550 nm and 1575 nm as a function of detector reverse bias voltage. The measured internal quantum efficiency is in the range of 50 % to 55 % with bias voltages between -2 to -4 V. The TE spectral response is shown in Fig. 3(b). The edge of the spectral response red-shifts with increased reverse bias, while the absorption at the shorter wavelengths slightly deceases due to the quantum confined stark effect [9].
Fig. 3. (a). Quantum efficiency as a function of reverse bias at 1550 nm and 1575 nm (b) Spectral response for TE polarization.
The I-V curve of the device is shown in Fig. 4(a). The dark current is between 50 nA to 400 nA with a bias range of -1V to -4 V. The dark current can be reduced further by removing the native indium oxide layer along the III-V mesa sidewalls before applying the SU-8 layer. The 80 ohm series resistance beyond diode turn-on (0.8 V) is due to the thin n-layer and the contact resistances. The device capacitance was measured using a C-V meter as a function of reverse bias as shown in Fig. 4(b). The capacitance is 0.3 pF under zero bias and decreases down to 0.17 pF as the reverse bias increases. This agrees with capacitance calculated for a III-V mesa of this size (2 μm × 100 μm). The parasitic p-pad capacitance with a SU-8 layer (5 μm thick and εr=3.28 at 1GHz) is negligible. The estimated RC limited bandwidth is 7.5 GHz calculated based on the measured capacitance and the series resistance with 50 ohm load.
The amplifier chip gain is measured by taking the ratio of the input power and output power of the amplifier and is shown in Fig. 5. The input power of the amplifier is estimated by taking account for a fiber coupling loss of 5 dB. The output power of the amplifier is measured by multiplying the photocurrent and its responsivity which can be directly converted from the measured quantum efficiency. The maximum chip gain is 9.5 dB at 300 mA for both wavelengths of 1550 nm and 1575 nm and doesn’t increase beyond 300 mA because of device heating. This gain is lower than the previously reported value of 13 dB chip gain [8] because of additional losses at the III-V tapers and a shorter amplifier length. The gain peak occurs at 1575 nm and the 3 dB gain bandwidth is ~60 nm at 300 mA as shown in Fig. 5(b). The transverse magnetic (TM) gain and responsivity of the receiver is lower than TE polarization because of the lower TM gain and absorption coefficients of the compressively strained quantum wells. The polarization dependence of individual devices had been reported in Refs. 7 and 8.
Fig. 5. (a). The amplifier chip gain as a function of the current at 1550 nm and 1575 nm (b) The amplifier gain spectrum with three different currents. The chip gain shown here is for TE polarization.
The ASE spectra from the amplifier are shown with three different currents in Fig. 6(a). The tapered junction reflectivity is estimated by measuring the ripples of the Fabry-Perot response of the amplifier ASE. Although the ASE spectrum shows no clear Fabry-Perot cavity response, the maximum ripple due to noise at 300 mA (a chip gain of 9.5 dB) is 0.1 dB which corresponds to a maximum reflectivity of 6×10-4. Non-tapered amplifiers with 7° tilted III-V junctions were also fabricated and tested. They exhibited a reflectivity of ~5×10-3. To estimate the loss from the III-V taper, the responsivity of the amplifier under the reverse bias is analyzed. The responsivity of the amplifier under the reverse bias is measured to be 1.06 ~ 1.15 A/W in the wavelength range of 1530 nm to 1580 nm and this corresponds to 86 % ~ 90% quantum efficiency. Since the amplifier is long enough to absorb all of the light coupled to the hybrid waveguide in the short wavelength range, this indicates that the taper loss is ~0.6 dB for this particular device [Fig. 6(b)] and it is typically 0.6 dB ~ 1.2 dB. The inset of Fig. 6(b) is the calculated taper loss with different taper lengths using two different commercial simulation tools, Fimm Wave [10] and Beam Prop [11]. The fabricated taper length is 70 μm long and the additional loss in the measured taper can be attributed to the side wall roughness and the blunt tip of the taper.
Fig. 6. (a). ASE spectra of the amplifier (b) estimated III-V taper loss (inset) calculated III-V taper loss with different taper lengths.
Figure 7 shows the saturation characteristics of the receiver at 1550 nm. The chip gain of the amplifier is 9.5 dB and the reverse bias voltage of the detector is -4 V. The x-axis of the graph shows the coupled input power taking into account the 5 dB coupling loss. The overall responsivity of the receiver before saturation is 5.7 A/W and the device is saturated by 0.5 dB at an output photocurrent of 25 mA. The dark current of the receiver due to the ASE noise from the amplifier is 25 μA at an amplifier current of 300 mA.
The impulse response of the detector is measured by launching 600 fs short pulses with a 20.1 MHz repetition rate from a mode-locked fiber laser to input 2. A 40 GHz RF probe connected to a 26 GHz bias-tee is used to collect the photo current. The signal is fed into a 50 GHz digital communications analyzer to sample the pulse. The response exhibits a rising time (10%-90%) of 18 ps. The long tail of the response indicates the carrier transport, especially for holes, limits the device bandwidth. The Fourier transform of the impulse response is shown in the inset of Fig. 8 and the 3 dB bandwidth is estimated to be 3 GHz. The current quantum wells have a valance band offset of ~105 meV between the well and the barrier, which causes hole trapping and electrical field screening [12]. A higher bandwidth can be achieved by using quantum wells with smaller valence band offset and a thinner SCH layer to reduce the hole transit time.
Fig. 9. (a). Eye diagrams of 2.5 Gb/s and 5 Gb/s PRBS input signal. (Top) with the amplifier (bottom) without the amplifier (b). Bit error rate curves measured with 231-1 NRZ 2.5 Gb/s transmissions with different amplifier gains.
Figure 9(a) shows eye diagrams measured at non-return-to-zero (NRZ) 2.5 Gb/s and NRZ 5 Gb/s with a 50 ohm termination and 37 dB electrical amplification. The top two eye diagrams are measured after the signal is amplified (9.5 dB gain) through input 1 while the bottom two eye diagrams are directly detected without amplification by launching the signal to input 2 [See Fig. 1(a)]. The quality factors (Q factors) of the eye diagrams detected without the amplifier is slightly higher than the ones after the amplification at the same photo current level, e.g. 7.7 vs 8.4 for 2.5 Gb/s PRBS, because of the additional ASE noise. The eye diagrams are open for modulation up to 5 Gb/s NRZ.
The bit error rate (BER) was measured with 2.5 Gb/s NRZ 231-1 pseudorandom bit sequence (PRBS) with different amplifier gains and the result is shown in Fig. 9(b). The purple data points are baseline measurements without the amplification by launching the signal to input 2. The BER data at an amplifier current of 100 mA shows worse receiver sensitivity than the receiver sensitivity without amplification (baseline) because the amplifier operates below the transparency. Once the amplifier is driven beyond transparency, the power penalty becomes negative as shown in the three BER curves on the left side. At the maximum gain of 9.5 dB, the power penalty is -8.5 dB compared to the baseline and the receiver sensitivity at a BER of 10-9 is -17.5 dBm. The 1 dB difference between the gain and the measured power penalty is due to the ASE noise. This is slightly higher than the previously reported power penalty of 0.5 dB because of lack of a bandpass filter [13]. Better sensitivities would be achievable with a good transimpedance amplifier.
4. Conclusion
The integration of a hybrid silicon evanescent amplifier and a hybrid silicon evanescent detector has been demonstrated. The individual amplifier and detector have a maximum gain of 9.5 dB and an internal quantum efficiency of 55 % at 1550 nm. The total receiver responsivity is 5.7 A/W. The III-V taper used to minimize the reflection exhibited an excess loss of 0.6 dB and a reflection less than 6×10-4. The receiver sensitivity of the receiver is -17.5 dBm at 2.5 Gb/s PRBS data transmission and this is 8.5 dB better than the receiver sensitivity without the amplifier. A higher bandwidth can be achieved by reducing the quantum well valence band offset. This device can be integrated with silicon passive wavelength demultiplexers for high speed WDM receivers [14].
Acknowledgments
References and links
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