1. INTRODUCTION

Currently, field programmable gate arrays (FPGAs) are widely used for a variety of applications, for example, consumer electronics [1,2], automotive embedded systems [3,4], and so on. However, the miniaturization speed of very-large-scale integrations (VLSIs) supporting the advancement of FPGAs is slowing down because transistors are reaching atomic size [5,6]. Therefore, an alternative technology to increase the performance of FPGAs is necessary.

Therefore, currently, optically reconfigurable gate arrays exploiting optical technologies in addition to a VLSI technology are in development [7,8]. Optically reconfigurable gate arrays are multi-context FPGAs and support high-speed reconfigurations of their programmable gate arrays so that the performances of the programmable gate arrays can be increased. Since optically reconfigurable gate arrays exploiting a high-speed dynamic reconfiguration can achieve a higher performance than FPGAs, optically reconfigurable gate arrays are suitable for hardware accelerations, high-performance computing, personal computers, and so on [9]. Conventional optically reconfigurable gate arrays use a spatial-multiplexed thin two-dimensional holographic memory addressed by single-wavelength lasers.

This paper presents a proposal of an optically reconfigurable gate array using a colored configuration. The optically reconfigurable gate array consists of an optically reconfigurable gate array VLSI including a fine-grained programmable gate array, a holographic memory, and four lasers with different wavelengths. This paper presents the demonstration of the optically reconfigurable gate array using a colored configuration.

2. OPTICALLY RECONFIGURABLE GATE ARRAY USING A COLORED CONFIGURATION

The proposed optically reconfigurable gate array using a colored configuration is shown in Fig. 1. The optically reconfigurable gate array consists of an optically reconfigurable gate array VLSI including a fine-grained programmable gate array, a holographic memory, four lasers with different wavelengths, and beam splitters. Four configuration contexts are stored on the holographic memory as a wavelength-multiplex and can be addressed by the four lasers. The optically reconfigurable gate array VLSI has a number of photodiodes to receive an optical configuration context generated from the holographic memory, as shown in Fig. 2 and Table 2. In the optically reconfigurable gate array, four circuits are dynamically programmed onto the optically reconfigurable gate array VLSI so that the performance of the programmable gate array can be increased.

 

Fig. 1. Block diagram of an optically reconfigurable gate array using a colored configuration.

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Fig. 2. Photograph of a 0.18 μm CMOS process optically reconfigurable gate array VLSI.

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Table 1. Specifications of the ORGA-VLSI

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Table 2. Configuration Speed of a Full System Including Beam Splitters

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3. HOLOGRAPHIC MEMORY CALCULATION

Here, a holographic memory on an optically reconfigurable gate array is realized by using a liquid crystal spatial light modulator. The holographic memory pattern displayed on the liquid crystal spatial light modulator is treated as a two-dimensional thin holographic memory and is modulated as gray-level. The liquid crystal spatial light modulator can be considered as a programmable holographic memory. An aperture plane of four lasers, a holographic plane, and an optically reconfigurable gate array VLSI plane are parallelized, as shown in Fig. 1. Four collimated lasers, each having a different wavelength, are implemented. When the optically reconfigurable gate array satisfies the Fresnel region, the intensity of each pixel of a holographic memory pattern is calculable using the following equation:

The value $H_{\text{color}}(\alpha ,\beta )$ is normalized as 0–1 for the minimum intensity $H_{\min }$ and maximum intensity $H_{\max }$, as explained in the following:

4. OPTICALLY RECONFIGURABLE GATE ARRAY VLSI

A. Gate Array Design

An optically reconfigurable gate array VLSI was fabricated using a 0.18 μm standard complementary metal oxide semiconductor (CMOS) process technology. A chip photograph is portrayed in Fig. 2. A transmission gate cell and a photodiode cell were designed as custom cells. The gate array design was synthesized by combining such custom cells and standard cells. The logic synthesis tool is design compiler (Synopsys Inc.). A place and route for the synthesized gate array design was executed using Astro (Synopsys Inc.). Finally, the optically reconfigurable gate array (ORGA)-VLSI was fabricated at Rohm’s manufacturing facility. Table 1 presents the specifications. The voltages of the core and I/O cells were designed respectively using 1.8 V and 3.3 V. The junction of photodiodes was constructed between an N-well and a P-substrate. The junction area of a photodiode was designed as $4.40\mathrm{\mu m}\times 4.45\mathrm{\mu m}$. The photodiode aperture size is $6.08\mathrm{\mu m}\times 6.08\mathrm{\mu m}$. The photodiode cells are arranged at 30.08 μm horizontal intervals and at 30.24 μm vertical intervals. This design incorporates 10,322 photodiodes. The gate array of the ORGA-VLSI uses an island style. The basic functionality of the gate array is fundamentally identical to that of currently available FPGAs. In all, 80 optically reconfigurable logic blocks (ORLBs), 90 optically reconfigurable switching matrices (ORSMs), and eight optically reconfigurable I/O blocks (ORIOBs), which include four programmable I/O bits, were implemented into the gate array VLSI. The ORLBs, ORSMs, and ORIOBs are programmable respectively through 69, 49, and 49 optical connections. The total gate count is 2720.

B. Optically Reconfigurable Logic Block

Each optically reconfigurable logic block consists of 2 four-input one-output lookup tables (LUTs), 12 selectors, 8 tri-state buffers, and 2 delay-type flip-flops with a reset function. The input signals from the wiring channel, which are applied through some switching matrices and wiring channels from optically reconfigurable I/O blocks or optically reconfigurable logic blocks, are transferred to the LUTs through eight selectors. The LUTs are used for implementing Boolean functions. The outputs of an LUT and of a delay-type flip-flop connected to the LUT are connected to a selector. A combinational circuit and sequential circuit can be chosen by changing the state of the selector, as in FPGAs. The programming is also executed optically. The cell size is $288.00\mathrm{\mu m}\times 192.48\mathrm{\mu m}$. Finally, the output of the selector is connected to a wiring channel again through eight tri-state buffers. In all, 69 photodiodes are used for programming an optically reconfigurable logic block. The optically reconfigurable logic block is perfectly reconfigurable in parallel. Such an optically reconfigurable logic block design is based on a standard cell design, except for custom cells of the transmission gate cells and photodiode cells.

C. Optically Reconfigurable Switching Matrix

Its basic construction is the same as that used by Xilinx Inc. Four-directional switching matrices with 48 transmission gates were implemented in the gate array. Each transmission gate can be regarded as a bi-directional switch. A photodiode is connected to each transmission gate. It controls whether the transmission gate is closed or not. The four-direction switching matrices can be programmed using 49 optical connections. The cell size is $197.76\mathrm{\mu m}\times 192.48\mathrm{\mu m}$. Such an optically reconfigurable switching matrix was designed using custom cells of photodiode cells and transmission gate cells, except for some buffers.

5. EXPERIMENTAL SYSTEM

In order to demonstrate the optically reconfigurable gate array using a colored configuration shown in Fig. 1, we have first constructed four optical systems without beam splitters. The block diagrams of the optical systems with a 404 nm blue laser, a 532 nm green laser, a 632.8 nm red laser, and a 642 nm red laser are shown in Figs. 3(a)–3(d), respectively. Also, the photographs of the optical systems are shown in Figs. 4(a)–4(d). All lasers were collimated. The powers of a 404 nm blue laser, a 532 nm green laser, a 632.8 nm red laser, and a 642 nm red laser are 80, 300, 30, and 100 mW, respectively. Each optical system consists of a liquid crystal spatial light modulator, a laser, and an optically reconfigurable gate array VLSI. For different colored reference beams, an AND circuit, an OR circuit, an EXOR circuit, and a NOR circuit were implemented onto a holographic memory. The holographic memory pattern was calculated as shown in Fig. 5 by using a personal computer. The AND circuit, the OR circuit, the EXOR circuit, and the NOR circuit can be read from the holographic memory by using 404, 532, 632.8, and 642 nm reference beams. The holographic memory pattern was displayed on a liquid crystal spatial light modulator (L3D07U-81G00; Seiko Epson Corp.) in the four optical systems. The panel consists of $1920\times 1080$ pixels, each having a size of $8.5\mathrm{\mu m}\times 8.5\mathrm{\mu m}$. The holographic memory pattern used $350\times 350$ pixels. The other pixels were programmed to opaque. The configuration contexts were programmed onto a 0.18 μm CMOS process optically reconfigurable gate array VLSI. The optically reconfigurable gate array VLSI was located 160 mm behind the liquid crystal spatial light modulator in the four optical systems.

 

Fig. 3. Block diagram of experimental systems. (a) Blue laser ($\lambda =404\text{\hspace{0.17em}nm}$), (b) green laser ($\lambda =532\text{\hspace{0.17em}nm}$), (c) red laser ($\lambda =632.8\text{\hspace{0.17em}nm}$), and (d) red laser ($\lambda =642\text{\hspace{0.17em}nm}$).

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Fig. 4. Photograph of the experimental systems. (a) Blue laser ($\lambda =404\text{\hspace{0.17em}nm}$), (b) green laser ($\lambda =532\text{\hspace{0.17em}nm}$), (c) red laser ($\lambda =632.8\text{\hspace{0.17em}nm}$), and (d) red laser ($\lambda =642\text{\hspace{0.17em}nm}$).

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Fig. 5. Color holographic memory pattern recording four configuration contexts of an AND circuit, an OR circuit, an EXOR circuit, and a NOR circuit respectively responding to a 404 nm laser, a 532 nm laser, a 632.8 nm laser, and a 642 nm laser.

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Moreover, we have also constructed a full optically reconfigurable gate array including beam splitters. The block diagram and photograph are shown in Figs. 6 and 7, respectively. The colored reconfiguration performance has been estimated by using the full optically reconfigurable gate array.

6. EXPERIMENTAL RESULTS

First, the reconfiguration procedure of the optically reconfigurable gate array using a colored configuration has been demonstrated using the above experimental systems not using beam splitters. The reconfiguration signals of the optically reconfigurable gate array VLSI were controlled by a field programmable gate array (APEX20KC EP20K200C8; Altera Corp.). The CCD captured configuration contexts of an AND circuit, an OR circuit, an EXOR circuit, and a NOR circuit are shown in Figs. 8(a)–8(d), respectively, corresponding to 404, 532, 632.8, and 642 nm reference laser beams. The configuration patterns were programmed onto the optically reconfigurable gate array VLSI. In addition, the waveforms of the AND circuit, the OR circuit, the EXOR circuit, and the NOR circuit are shown in Figs. 9(a)–9(d), respectively, which were measured using a 2 GHz 16903A Logic Analysis System including a 68 Channel 4 GHz Timing/600 MHz State Logic Analysis Module (16950A; Agilent Technologies Inc.). The reconfiguration speeds of 404, 532, 632.8, and 642 nm lasers were 110.6 μs, 21.29 μs, 1241 μs, and 158.1 μs. Moreover, the colored reconfiguration procedure was demonstrated using the full optically reconfigurable gate array including beam splitters. The experimental results are shown in Table 2. The reconfiguration speeds of 404, 532, 632.8, and 642 nm lasers were 791.2 μs, 291.9 μs, 179.0 μs, and 568.8 μs. We have confirmed that all configuration procedures were correctly executed.

 

Fig. 6. Block diagram of the experimental system.

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Fig. 7. Photograph of the experimental system.

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Fig. 8. CCD-captured configuration context patterns of an AND circuit, an OR circuit, an EXOR circuit, and a NOR circuit addressed by (a) 404 nm, (b) 532 nm, (c) 632.8 nm, and (d) 642 nm lasers, respectively.

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Fig. 9. Waveforms of (a) AND circuit, (b) OR circuit, (c) EXOR circuit, and (d) NOR circuit operations on the optically reconfigurable gate array VLSI.

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The reconfiguration speeds depend on the wavelength and the power of the lasers. For example, when a photodiode on the optically reconfigurable gate array VLSI receives 1 nW light with a 404 nm wavelength, a 532 nm wavelength, a 632.8 nm wavelength, and a 642 nm wavelength, the response times of the photodiode are 62.859 μs, 41.785 μs, 36.044 μs, and 28.392 μs, respectively. The peak of sensitivity of pn junction photodiodes is always in infrared. Normalizing the power of the 642 nm laser to 1 when a certain reconfiguration operation is executed, in the cases of 404 nm, 532 nm, and 632.8 nm lasers, 2.214, 1.472, and 1.270 times higher powers are necessary, respectively, to realize the same configuration speed as the 642 nm laser. However, even if there is such wavelength dependence in the pn junction photodiode, all reconfiguration speeds are sufficiently faster than several hundred milliseconds of field programmable gate arrays.

However, comparing it with previous works [7,8], the reconfiguration speed is not fast. Two four-configuration-context optically reconfigurable gate arrays have been proposed. Their reconfiguration times were reported as 812–1000 ns in the case of a 532 nm 300 mW laser [7] and 3.4–11.5 μs in the case of a 632 nm 30 mW laser [8]. Therefore, the reconfiguration speeds of previous optically reconfigurable gate arrays are superior to the reconfiguration speed of this work.

However, the advantage point of this architecture is to increase the number of configuration contexts by combining it with the previous works. Although the current system uses beam splitters and collimated laser beams, the future system will use diffusion beam lasers, which can be considered as point sources of light. In this case, we will be able to implement a lot of lasers at slightly different positions on a holographic memory region so that the beam splitters can perfectly be removed. Power loss demerit on beam splitters will be removed and the number of lasers or configuration contexts can easily be increased. In this demonstration, 642 nm and 632.8 nm lasers, the wavelengths of which are very close to each other, were used. Even so, the correct multi-configuration procedure could be executed. Therefore, since close wavelength lasers can be applied for this system, the number of lasers or configuration contexts is easily increased. Moreover, combining this work with the previous works, a single holographic memory region can include four configuration contexts and moreover, the number of regions can be increased to four so that 16 configuration contexts can be implemented onto an optically reconfigurable gate array. A combination of the colored configuration and previous multi-context configuration is very useful to increase the number of configuration contexts.

7. CONCLUSION

This paper has presented a proposal of an optically reconfigurable gate array using a colored configuration. We have used four lasers with different wavelengths for the optically reconfigurable gate array and have experimentally confirmed that the four colored reconfiguration procedures using a single holographic memory can be executed correctly. The reconfiguration speeds were faster than those of field programmable gate arrays. This paper has presented that the wavelength-multiplex of the colored configuration is useful for reading of the holographic memory in addition to a spatial-multiplex in optically reconfigurable gate arrays.